ModelSim -> Error: xxxxx.vhd(n): Library yyyy not found - Page 2

Altera_Forum · ‎10-02-2011

I'm trying to run an RTL Simulation of a project using the NativeLink set-up in Quartus II. But I end up with the following error: (in red)

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Reading C:/altera/11.0sp1/modelsim_ase/tcl/vsim/pref.tcl

# do GrabReader_run_msim_rtl_vhdl.do

# if {[file exists rtl_work]} {

# vdel -lib rtl_work -all

# }

# vlib rtl_work

# vmap work rtl_work

# Copying c:\altera\11.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini

# Modifying modelsim.ini

# ** Warning: Copied c:\altera\11.0sp1\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.

# Updated modelsim.ini.

#

# vcom -93 -work work {C:/qdesigns/c-cam/bb/vhdl_packages/CC_Data_Types.vhd}

# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package numeric_std

# -- Loading package math_real

# -- Loading package lpm_components

# -- Compiling package cc_data_types

# -- Compiling package body cc_data_types

# -- Loading package cc_data_types

# vcom -93 -work work {C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd}

# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010

# -- Loading package standard

# -- Loading package std_logic_1164

# -- Loading package lpm_components

# ** Error: C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd(7): Library cc_data_types not found.

# ** Error: C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd(8): (vcom-1136) Unknown identifier "cc_data_types".

# ** Error: C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd(11): VHDL Compiler exiting

# ** Error: c:/altera/11.0sp1/modelsim_ase/win32aloem/vcom failed.

# Error in macro ./GrabReader_run_msim_rtl_vhdl.do line 9

# c:/altera/11.0sp1/modelsim_ase/win32aloem/vcom failed.

# while executing

# "vcom -93 -work work {C:/qdesigns/c-cam/bb/gates/regmux/regmux.vhd}"

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So Modelsim doesn't seem to find a package in a lower module, although it had no problem locating it just a bit earlier.

If I run the Gate Level Simulation everything runs OK, except that I don't get a clock running.

	genclk : process
		begin
			Clk <= '0' ;
			wait for TClChClk ;
			Clk <= '1' ;
			wait for TClChClk ;
		end process genclk ;

For building Lower level modules a Gate Level Simulation is not really necessary, so I tried the RTL Simulaton.

Any clues?

Altera_Forum · ‎11-20-2011

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Argh, that's a horrible thing to do :)

Do you rebuild the lpm library, and altera_mf library, etc., every time you run Modelsim? No of course you don't. How then does Modelsim Altera know about these libraries ... through the magic of library mappings.

Think of Modelsim libraries as shared object libraries, like a DLL or .so file.

When you build a C program or C++ program, you link against the shared library, you do not build it each time.

The same analogy holds for Modelsim libraries (whether the language be VHDL or Verilog - VHDL just happens to be more specific about their use).

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Why? Of course I do not recompile every .DLL (most often we do not have the source anyway ...) I too like the CC_Data_Types as the name of the library better, but I can live with the work-surrogate, as the package in question is only predefined types, procedures and functions and not 'actual' RTL.

Normally I do timing simulation anyhow (using the internal Quartus simulator or now ModelSim) but I figured that RTL simulation might run faster so I tried to solve the 'missing package'. As we don't have to do a full compile for RTL simulation I might switch to another editor (very probably Sigasi) and then use the script method to run ModelSim.

Regards,

Josy