ModelSim "True Dual Port" Memory viewer weird

[Altera_Forum]

Hi everyone. 

 I have a question for you all.  I have a FPGA VHDL design using Cyclone III, in my design I used internal memory configured as true dual port RAM. I created the VHDL code, simulate it in ModelSim and waveform looks fine. But if I tried to view internal memory content, I found something weird. There are two memory list in memory list window, Port A memory and Port B memory. I can see the content of memory from Port A correctly but when I tried open window form Port B, all memory content become all "U".  I perform simulation to write memory through port B and read data written from Port A. Functional simulation show all fine. I just don't understand why memory viewer for Port B become all "U". Is there someone here know why this is happened? Is there something incorrect in my simulation or my design?   Thanks, any kind of help will be appreciated... :D

[Altera_Forum]

Are you of course reading port B after you've written it, right? 

In the meanwhile you're not writing the same location you're reading, true?

[Altera_Forum]

No, I write data into Port B, after writing sequence finished then I read data inside memory from Port A. So I don't read data being written in the same time. 

 Darkwave, do you have any idea? thanks,...

[Altera_Forum]

I've not maybe understood the problem. 

You told: "I write data into Port B, after writing sequence finished then I read data inside memory from Port A. So I don't read data being written in the same time." and before "I can see the content of memory from Port A" that is right since you're writing data on port B and reading from port A. Moreover there is no problem at all as you've stated..  What do you mean when you tell "when I tried open window form Port B"?  What are you using for simulate it? Internal Quartus II simulator that is present until v9.1 or maybe Simulink with a vhdl/verilog testbench?

[Altera_Forum]

I wouldnt be surprised if it only used the port A storage - it is stored in a variable inside a process in the code. On the real hardware there is only 1 memory area for the two ports anyway. If "m_mem_data_b" is always 'U', it just means it is never assigned anything - if your design is working then Im presuming it only ever puts data into "m_mem_data_a". This models realistic behaviour. 

 if it works, dont worry.

[Altera_Forum]

Hi darkwave,  

On ModelSim simulation window, on the left side, there is memory tab, it is internal memory viewer for simulation. On it's tab, there are two list, it is m_mem_data_a (for port A) and m_mem_data_b(for port B ), when I said "I tried open window form Port B" I mean I clicked the m_mem_data_b so a windows displaying the content of internal memory appear.  I use ModelSim with VHDL testbench.  Hi Tricky, So It is for modeling only. Now I don't worry again.  Anyway, Thanks for both of you. I appreciate all of your help...:) :) :)

[DogZapper]

So, I got this same issue.  According to what I read above, I'm just suppose to ignore the data contents of all "U"s in memory B.  Then why does modelSim even produce a memory_B?  I have some code that is not working and I'm trying to fix it.  I thought maybe I had a memory issue, but maybe not?  I don't understand modelSim's depiction of memory using  A&B outputs?