[ModelSim simulation problem] $hold??

[Altera_Forum]

Hi ~there, 

 I'm using ModelSim to do a simulation about viterbi decode simulation. I use Verilog HDL and FPGA and the device is one of altera cyclone III series . But unfortunately a problem happens, like this :   Error: C:/altera/72/modelsim_ae/win32aloem/../altera/verilog/src/altera_primitives.v(287): $hold( posedge clk &&& nosloadsclr:2315 ps, d:2415 ps, 186 ps );# Time: 2415 ps Iteration: 3 Instance: /ViterbiDecoder_vlg_tst/i1/\SMU|DataOutEnBuf_rtl_0|auto_generated|cntr1|counter_reg_bit[4]  I don't know where this "$hold" come from and what is it used for.I have checked all the codes and there isn't any problem and Quartus II has complied successfully.It's upset me for a few days and still find no way to solve it.  Do you smart guys have been encountered this problem before ? How did you solve it ? I'm looking forward to your help! Thanks!  Vivi