Modelsim Altera Starter & .tb

[Altera_Forum]

Hi , 

 I use modelsim Altera starter 10.1b unlicensed and i can't use testbench file and simulate. My simulation is good when i use "simulate without optimization" and not with "simulate" . I need license to use testbench file and "simulate"??  Thanks   Polyced  PS:I apologize for my poor English

[Altera_Forum]

For ModelSim-Altera Starter-Edition, you wont need a license to simulate (it's free of charge). Have you tried simulating it using Nativelink rather than doing it manually?

[Altera_Forum]

yes when i run RTL simulation , i have this info in quartus : 

 Info (22036): Successfully launched NativeLink simulation (quartus_sh -t "c:/altera/12.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "test_pll" "test_pll_top") Info (22036): For messages from NativeLink execution see the NativeLink log file D:/Projets electronique Quartus/Test_pll/test_pll_nativelink_simulation.rpt Info (22036): Successfully launched NativeLink simulation (quartus_sh -t "c:/altera/12.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "test_pll" "test_pll_top") Info (22036): For messages from NativeLink execution see the NativeLink log file D:/Projets electronique Quartus/Test_pll/test_pll_nativelink_simulation.rpt Info (22036): Successfully launched NativeLink simulation (quartus_sh -t "c:/altera/12.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl" -gate_netlist "test_pll_top.vho" -gate_timing_file "test_pll_top_vhd.sdo" "test_pll" "test_pll_top") Info (22036): For messages from NativeLink execution see the NativeLink log file D:/Projets electronique Quartus/Test_pll/test_pll_nativelink_simulation.rpt  I think i use NativeLink. I want create a testbench file to no always create my input signal.  In my first , i create manually my input siganl and export waveform in vhdl testbench. In assignments/settings .../ simulation /compile testbench  But i run rtl simulation error loading?

[Altera_Forum]

From the message, it says "Successfully launched NativeLink simulation". Did ModelSim window come out? Have you set the location of ModelSim in your EDA tools options (Tools-->Options --> EDA Tool Options). Could you describe more about the problem you're facing now?

[Altera_Forum]

Yes modelsim window come out , and location of modelsim. 

 Now i want to simulate altpll with RTL and gate level. When i simulate with gate level (or rtl) my result is bad (see attached room). I modifie parameters and always same result. And i don't want always create my input signal.   I want create a testbench file to create input file once. (see attached room)  i assign test bench file in "assignments/settings .../ simulation /compile testbench " (see attached room) And i run gate level : message : error loading design (see attached room)   I hope you understand my probleme and you can help me.  Thanks