Modelsim design size limit buggy and or misleading in Quartus Lite 19.1

[RH0001]

Hi, I am trying to simulate a small design totaling just 1025 lines of VHDL including the Megawizard parts & test bench YET Modelsim prints a warning

# ** Warning: Design size of 17912 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.

# Expect performance to be adversely affected.

And goes into totally slugged mode making itself unusable.

Why is there such a large discrepancy between the actual size of the design and that claimed by modelsim ? Is this a bug ?

The Megawizard parts are a PLL and two small block rams, the rest of the code consists of a top module joining two lower level modules, then of course there is a small test bench.

Has anybody else experienced this problem ?

[AnandRaj_S_Intel]

Hi RH,

It is not a bug.

ModelSim-Intel FPGA Starter Edition Software has 10,000 executable line limitations.

The number of line count included all the design files, IP & libraries.

Solution

1. Optimize your design by emove your Megawizard Ip
2. Use ModelSim-Intel FPGA Edition Software.

.

Regards

Anand

[RH0001]

Hi Anand

Thank you for your answer, I understood the limit did not include all the pre-compiled libraries of which there are a huge collection.

Is there a way for me to remove the libraries for all the chips I am not using (about 90%) ?

Regards

RH

[AnandRaj_S_Intel · Accepted solution]

Hi RH,

I meant file in ModelSim work libraries.

1. Reduce the size of the design (remove the ram and check)
2. Neglect the warning, You can simulate the design but simulation may take time.
3. Upgrade to Modelsim from SE to FE

https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html

Regards

Anand

[RH0001]

OK many thanks for your help, it's like 20 years ago, just leave a simulation running all night haha