I have a code which compiles correctly but when I simulate it using ModelSim, it gives me this warning:
Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
I would have ignored this warning but I think this causes my output signal to be U all the time , not only at the beginning.
I am attaching my code here. Sorry for the size of the code.
If anyone could please suggest what is going wrong, it will be a big help.
I am getting the same error in almost all the files (code) which are related to my main project.
Thank you in advance.
"I have a code which compiles correctly but when I simulate it using ModelSim, it gives me this warning:"
code which provided is not as per proper syntax especially library & architecture but I assume that, you could have compiled it correctly since you mentioned it. please refer the attached VHDL language reference manual for proper syntax.
if you compiled design(DUT) successfully then initialize all the inputs & outputs in test bench, the warning which you got it`s might be because of not initialization of Inputs& outputs.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
(This message was posted on behalf of Intel Corporation)
Thanks for your reply.Yes I have compiled the design successfully and then initialized the inputs and outputs. in the test bench.
I think I should be initializing the output as well ( which I have not done). Will this cause the output to be in uninitialized state all the time
throughout the execution of the code?
I already informed that, the code which you provided is not as per syntax & has number of errors. so I asked to you provide successfully compiled code in my last post.
(This message was posted on behalf of Intel Corporation
Outputs that are U have to come from somewhere. You need to use the simulator to follow the signals back from the output to discover what signals are uninitialised. Then you either give them an initial value or decide it is not important ( maybe there is a valid signal that marks the data as invalid anyway).
Modelsim can be set to ignore warnings like this from IEEE packages. It is a simulation setting.
The code I provided is compiling successfully. It includes an IP which I have not included in the code attached.
Can you please tell me what are the syntax errors in my code. May be that might help me.
Thank you for your suggestions.
I have implemented your second suggestion of suppressing warnings from IEEE packages in the simulation settings.
Let me try tracing back the output signal and see which signals are uninitialized.
I will post my findings here.
This might lead me somewhere.
Thank you once again.