Modelsim.ini setting

[junyoung2]

Hello, I learned about a setting called vlog while searching for bit width mismatch.

I confirmed that if you set anything in the folder called Modelsim.ini, it will alert you when bit width does not match.

(For example, if you assign 8 bit signal B to 16 bit signal A / if you code assign [15:0] A = B)

Can Modelsim set up a setting that can detect these errors on its own? If so, how can I set it that way?

The version you are currently using is version 10.7b.

[KennyTan_Altera]

I have attempt to find some setting in the Questasim/Modelsim user guide, there are no option for this.

What I would suggest you is to go to EDA/Mentor Graphic forum to ask this question as this question is more related to them.

[KennyTan_Altera]

This seems to be same question on https://community.intel.com/t5/Intel-Quartus-Prime-Software/wire-assignment-in-verilog/m-p/1653904#M85097. We shall close this case.

[KennyTan_Altera]

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.