Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15469 Discussions

Modelsim –intel 10.5c reported a Fatal Error when I was simulating Intel FFT ip core

User1582192733150209
288 Views

Hello Sir/Madam,

 

Basic Information Quartus prime pro 17.1 + Modelsim-Intel Starter edition 10.5c +Arria10gx

 

I generated an Intel FFT ip core, because  option to generate a design example is in grey color and not available to choose on IP platform designer.

,so I have make my own one, I have installed 1 fft and ifft into my top level design. Acturally ,I was trying to duplicate the example I downloaded from Intel forum, but example uses different version and different device .

 

Because design also has rom and counter unit, so I have to to manually compile them into work library in modelsim.

 

1,source tcl msim_setup.tcl

2, ld

3, manually add top level signals of testbench into waves window

4,run –a

5,check the waveform, I can see the many signals are working as I expected, but suddenly stop in below stage

 

The error part is not my design, and it seems the low level library being called by upper design, I have no idea how to to fix them.

I have close the modelsim,  restart ,computer and simulated it again, got exactly same result as before.

# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE

#   Time: 180 ns Iteration: 1 Instance: /a_tb/DUT/u0/fft_ii_0/auk_dspip_r22sdf_top_inst/r22sdf_core_inst/gen_natural_order_core/gen_stages(0)/r22_stage/gen_bfi/bfi_inst/bf_control_inst

# ** Fatal: (vsim-3421) Value 5 is out of range 0 to 4.

#   Time: 180 ns Iteration: 1 Process: /a_tb/DUT/u0/fft_ii_0/auk_dspip_r22sdf_top_inst/r22sdf_core_inst/gen_natural_order_core/gen_stages(0)/r22_stage/gen_bfi/processing_bfi_cnt_p File: ./../../../../myfft/altera_fft_ii_171/sim/mentor/auk_dspip_r22sdf_stage.vhd

# Fatal error in Process processing_bfi_cnt_p at ./../../../../myfft/altera_fft_ii_171/sim/mentor/auk_dspip_r22sdf_stage.vhd line 803

 

Any suggestion is welcome

 

Jim

error1.JPG

 

error2.JPG

0 Kudos
1 Reply
SyafieqS
Moderator
226 Views

Hi Jim,

My first debug step would be, go to auk_dspip_r22sdf_stage.vhd line 803, figure out which variable is implicated and adjust its declaration range. This may fix the problem or cause another. But it might give you a clue.

 

Thanks,

Regards

Reply