Re: Modelsim won't compiles VHDL -> Unexpected signal: 11

Altera_Forum · ‎12-17-2015

Hi Altera,

some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code.

library ieee;
use ieee.std_logic_1164.all;
entity x is
generic (signal_count         : natural := 1);
port (clock : in std_logic);
end entity;
architecture rtl of x is
type t_signal_array is array (signal_count - 1 downto 0) of std_logic_vector (2 downto 0);
type reg_mclk_t is record
   ddr_chain : t_signal_array;
   output    : std_logic_vector(signal_count - 1 downto 0);
end record;
signal mclk_r     : reg_mclk_t;
signal mclk_r_in  : reg_mclk_t;
begin
MCLK_PROC: process (clock, mclk_r_in)
begin
if rising_edge (clock) then
   mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in#  ** Fatal: Unexpected signal: 11.
   --mclk_r.ddr_chain(signal_count - 1 downto 0) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0);       -- this works
   --mclk_r.ddr_chain(signal_count - 1 downto 0)(1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(1); -- this works
   --mclk_r.ddr_chain(signal_count - 1 downto 0)(2) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2); -- this works
   mclk_r.output <= mclk_r_in.output;
end if;
end process;
end rtl;

Syntax checking passes all verifications, but when it comes to writing the library data to file system compile process stops with following message.

--- Quote Start ---

# vcom -work work -2002 -explicit -stats=none C:/work/VHDL-Sims/Test_unexpectedSignal.vhd# Model Technology ModelSim ALTERA vcom 10.3c Compiler 2014.09 Sep 20 2014# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity x# -- Compiling architecture rtl of x# ** Fatal: Unexpected signal: 11.# ** Error: C:/work/VHDL-Sims/Test_unexpectedSignal.vhd(34): VHDL Compiler exiting

--- Quote End ---

Library view of ModelSim shows the new entity inside the library. However elaborating this entity and loading it into a simulation fails.

Even the library files on disk won't be created, thus elaboration can't find them.

Is there a specific reason for this or is it just a bug in ModelSim?

Altera_Forum · ‎12-17-2015

Looks like a Modelsim bug. Fatals like that without a decent explanation usually are.

Have you tried 10.4c? (the latest version)

If it still fails with latest you need to raise a ticket with mentor (not altera)

Altera_Forum · ‎12-18-2015

Thank you for the clarification. I wasn't sure if modelsim altera edition is managed by altera or by mentor.

I haven't got the 10.4c for now, but testing with 10.4b shows the same behavior.

Let's see what mentor says to this.

Altera_Forum · ‎12-18-2015

Ive compiled it in Questa 10.4c and 10.3c and didnt see a problem

Have you tried compiling in a clean folder?

How are you compiling the file?

Altera_Forum · ‎12-18-2015

Interesting that Questa doesn't have this problem.

So far i tried to compile it within a ModelSim project, outside a project file environment and into a clean newly created work library.

It doesn't changes the result and always comes up with the signal 11.

Only if i change the source from the double array range code to a single array access with individual bit access it compiles.

Altera_Forum · ‎12-18-2015

The questa ref manual gives exit 11 as "11 General language syntax error"

Altera_Forum · ‎12-18-2015

Again - this is a defect. You need to raise the issue with altera.

Altera_Forum · ‎12-18-2015

Ok thank you for your support. I just filed an service request to altera.