Hi Altera,
some Modelsim versions (10.3c and 10.1e) won't completely compile the following VHDL code.
library ieee;
use ieee.std_logic_1164.all;
entity x is
generic (signal_count : natural := 1);
port (clock : in std_logic);
end entity;
architecture rtl of x is
type t_signal_array is array (signal_count - 1 downto 0) of std_logic_vector (2 downto 0);
type reg_mclk_t is record
ddr_chain : t_signal_array;
output : std_logic_vector(signal_count - 1 downto 0);
end record;
signal mclk_r : reg_mclk_t;
signal mclk_r_in : reg_mclk_t;
begin
MCLK_PROC: process (clock, mclk_r_in)
begin
if rising_edge (clock) then
mclk_r.ddr_chain(signal_count - 1 downto 0)(2 downto 1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2 downto 1); -- this line results in# ** Fatal: Unexpected signal: 11.
--mclk_r.ddr_chain(signal_count - 1 downto 0) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0); -- this works
--mclk_r.ddr_chain(signal_count - 1 downto 0)(1) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(1); -- this works
--mclk_r.ddr_chain(signal_count - 1 downto 0)(2) <= mclk_r_in.ddr_chain(signal_count - 1 downto 0)(2); -- this works
mclk_r.output <= mclk_r_in.output;
end if;
end process;
end rtl; Syntax checking passes all verifications, but when it comes to writing the library data to file system compile process stops with following message.
--- Quote Start ---
# vcom -work work -2002 -explicit -stats=none C:/work/VHDL-Sims/Test_unexpectedSignal.vhd# Model Technology ModelSim ALTERA vcom 10.3c Compiler 2014.09 Sep 20 2014# -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity x# -- Compiling architecture rtl of x# ** Fatal: Unexpected signal: 11.# ** Error: C:/work/VHDL-Sims/Test_unexpectedSignal.vhd(34): VHDL Compiler exiting
--- Quote End ---
Library view of ModelSim shows the new entity inside the library. However elaborating this entity and loading it into a simulation fails.
Even the library files on disk won't be created, thus elaboration can't find them.
Is there a specific reason for this or is it just a bug in ModelSim?
