I'm trying to modify the a10_ref OpenCL BSP, specifically the a10gx_hostch board in 17.1. I'm trying to add IO channels for a 10GigE interface. I'm getting errors during the import compile I can't solve.
So far I've:
-added the 10GigE subsystem design to the board.qsys design
-generated the HDL for board.qsys
-added the physical constraints for the transceivers and reference clock to flat.qsf (using a single lane of the QSFP). I've taken these from arria10gx "golden" design.
-connected the source/sink streaming avalon signals from board_inst to freeze_wrapper in top.vhd
-connected the source/sink streaming avalon signals inside freeze_wrapper.v to kernel_system
-added the channels to board_spec.xml
-commented out most of the "logic lock regions" from base.qsf except for those pertaining to freeze_wrapp_inst. If I didn't do this fitter was running out of resources in various regions.
I call "aoc boardtest.cl" with ACL_DEFAULT_FLOW set to base. It fails when trying to generate the fpga.bin in the post_flow.tcl - but I think that's ok and it does generate base.qdb. I copy this base.qdb into the BSP hardware directory.
I then remove the ACL_DEFAULT_FLOW environment variable and call "aoc boardtest.cl" which I think invokes an "import compile". The compile fails in the fitter stage with a set of messages like below for all source/sink signals to the new IO channel:
Error (18514): Child partition "freeze_wrapper_inst|kernel_system_inst" expects its parent to drive input port "eth0_in_valid", but this port is not driven from its parent partition "|". Modify either the child or parent partitions so that all expected signals are correctly driven from the parent partition.
Error (18624): Partition "freeze_wrapper_inst|kernel_system_inst" contains output port "eth0_out_valid" that is ignored by its parent partition "|". Consider modifying your design so that all output ports are connected to their parent partitions.
My question is, how can I debug this? What does this error mean? I can open up kernel_system.qsys and see that the streaming interface (Avalon-ST Adapter) for eth0_in and eth0_out are present - even though the outptus are dangling and unused. It looks just like the host_to_dev and dev_to_host adapters for the host channel interfaces.
Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign someone to assist you. Thank you.
Yes, I was able to resolve the issue. Thank you for reaching out and responding. The porting to his new forum where there has been almost no support, elimination of support tickets, compounded with the limited user base for OpenCL development has been a big disappointment. 80% of my work is with Altera's direct competition and the comparison in support flow is NOT favorable to Intel right now.
Hi @SSFyTMT ,
Thank you for status update and its good to know you are able to resolve the issue. Appreciate the feedback, we will take note on this to channel the input accordingly. Please don't hesitate to post questions(wrt Intel FPGA) and continue to feedback as your input does help us improve or provide a better service within this forum. Hopefully you will experience a better support with us. Thank you.