Module Declaration Question for Transceiver Design

Altera_Forum · ‎11-15-2016

Hi, I was hoping someone could answer a fairly simple question. Here is my module declaration code for a transceiver design:

module xcvr_prbs (

//inputs

input wire phy_mgmt_clk,

input wire pll_ref_clk,

input wire reset_reset,

input wire reconfig_reset,

input wire rx_serial_data,

input wire rx_seriallpbken,

input wire xgmii_tx_clk,

input wire rx_serial_data_0,

input wire xgmii_tx_dc_0[71:0],

output wire xgmii_rx_clk,

output wire rx_data_ready,

output wire xgmii_rx_dc_0[71:0],

output wire tx_serial_data_0,

//ouputs

output wire errorFlag,

output wire [100:0] errorCount,

output wire tx_serial_data,

output wire tx_ready,

output wire rx_ready,

output wire [63:0] prbs_data_rx_top

);

My question is, how do I know whether to put input/output wires and registers inside the module parenthesis, or outside the parenthesis? I have been following some example transceiver designs and in those examples, some wires are declared inside and some outside. I am assuming the ones declared inside the module also need pin assignments. Is that correct?

Thanks in advance!

Altera_Forum · ‎11-16-2016

There are two styles of module header declarations; one from Verilog-1995 where you might have to mention a port name up to three times, and the one you are using from Verilog-2001 and later where everything is in one place.

See http://stackoverflow.com/questions/12229477/why-are-output-nets-also-required-to-be-redeclared-as-either-wire-or-reg

Altera_Forum · ‎11-17-2016

Thanks for the response. However, in my design, there are single declarations of different variables, not multiple declarations of the same variable; some are declared inside the parenthesis, some are outside. At least, this is what the native phy example I am following does and I am not sure how to decide what variables to declare inside and outside the module declaration.