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Valued Contributor III
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Question about component and packag

Hello, I am new to VHDL. I have a question about using a component in the package body which is defined in package head. But there is error about the port map in the package body. Could anyone help me on this? Thanks. 

the code is something like following: 

 

library ieee; use ieee.std_logic_1164.all; use work. comparator.all; package func_pkg is function compare (a, b: in std_logic_vector(3 downto 0)) return std_logic_vector(3 downto 0); component comparator port( in_a: in std_logic_vector(3 downto 0); in_b: in std_logic_vector(3 downto 0); alb: out std_logic ); end component; end package; package body func_pkg is function compare (a, b: in std_logic_vector(3 downto 0)) return std_logic_vector(3 downto 0) is variable result : std_logic_vector(3 downto 0); variable sig_l : std_logic; begin cmp: comparator port map (in_a => a, in_b => b, alb => sig_l); if (sig_l = '1') then result := a; else resutl := b; end if; end function; end package body; 

 

where comparator is the component which input a, b and return 1 if a<b.
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