Module logic use report as 0

[chipper]

Hi,

New to Quartus Prime.

I created several modules, but their reported logic use is 0, even though the modules are included in the RTL viewer and connect to IO. Is that normal, or does it mean something is wrong?

[FvM]

Hi,

there's something wrong, the modules have apparently no actual function in your design.

General rule: design logic will be discarded in synthesis if no output depends on it. Possible reasons: no output signals connected, missing clock, module stuck in reset.

[sstrell]

Yes, if you left stuff unconnected, it will get optimized away.