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Hi,
I have a design where an input is being oversampled by using multiple phase outputs from a PLL. To make this work I need to ensure that the skew between the input and each sampling register is at a minimum. I have tried using the set_max_skew constraint, but this seems to have no effect on the fitter results. Is there a known method for implementing this correctly using design constraints?
Thanks.
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Hi,
Does the skew value in the report_skew report less than the value you set using set_max_skew? Can you check if this constraint is being ignored and listed in the Ignored Constraints report? Have you tried setting the clock to global signal?
Thanks
Best regards,
KhaiY
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Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Best regards,
KhaiY
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