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Valued Contributor III
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Multiple Nios2 cores inside an FPGA?

Hello, 

Is it possible to have >1 Nios2 core inside a modern cyclone FPGA? And if so, can all the Altera development tools support this sort of platform? 

Thanks! 

Lefty
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Valued Contributor III
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In short: YES.

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Valued Contributor III
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Thanks for the fast reply! 

 

That sounds great. It would be a more mature technology to use than the SoC FPGA wouldn't it?  

All the problems (in the SW dev tools for example) will by now be pipe-cleaned out and also I can pick and choose amongst CycloneIII or IV for example? 

 

Are there any application notes/docs at Altera to specifically explain multi-core development?
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Valued Contributor III
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There was another similar question a few days ago... 

 

The advantage of SoC systems (and hard cpu on fpga) is that the cpu will run considerably faster than a Nios. 

OTOH the Nios is more flexible especially if you are integrating with other bespoke logic on the fpga. 

 

One of the reasons we've moved a lot of stuff into fpga is that they don't go obsolete in the same way as other components. 

Although the fpga itself might be obsoleted, a newer part will typically do the job and require limited rework rather than a complete redesign.
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Valued Contributor III
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Hello, 

Does the Cyclone IV have 2 NIOS on-board? I'm looking at the Cyclone IV but want 2 NIOS to work with. I've looked through data sheet and can't find a part number. 

Thanks
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Valued Contributor III
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Nios is a soft IP so definitely it will be available in Cyclone IV. You can even put in more than 2 Nios, as long as the logic resources are available.

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Valued Contributor III
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--- Quote Start ---  

Nios is a soft IP so definitely it will be available in Cyclone IV. You can even put in more than 2 Nios, as long as the logic resources are available. 

--- Quote End ---  

 

 

Thank you for the rely. In order to get 2 NIOS into the Cyclone IV, I had planned on using the largest IV FPGA which may be overkill but our requirements aren't quite set yet. Are he NIOS an IP that is instantiated into the design? How can I implement multiple NIOS? Thanks for your help.
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Valued Contributor III
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--- Quote Start ---  

Thank you for the rely. In order to get 2 NIOS into the Cyclone IV, I had planned on using the largest IV FPGA which may be overkill but our requirements aren't quite set yet. Are he NIOS an IP that is instantiated into the design? How can I implement multiple NIOS? Thanks for your help. 

--- Quote End ---  

 

 

In addition, If I use a large Cyclone III, would 2 or more NIOS fit?
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Valued Contributor III
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--- Quote Start ---  

In addition, If I use a large Cyclone III, would 2 or more NIOS fit? 

--- Quote End ---  

 

 

I think the easiest way to find out is to download Quartus, select a device (Cyclone III or IV), launch Qsys, and start to add Nios into your system. Then, compile to have a rough idea of the % logic utilization. Hopefully this can help you to make device selection easier. 

 

Note that Cyclone III is no longer supported in the latest Quartus release, but Cyclone IV is still supported.
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Valued Contributor III
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--- Quote Start ---  

How can I implement multiple NIOS? Thanks for your help. 

--- Quote End ---  

 

 

Using a reference design is the easiest way to get started :) download one from here: 

https://cloud.altera.com/devstore/platform/16.0.0/creating-multiprocessor-nios-ii-systems-design-exa... 

 

This is for Cyclone V but you can make the necessary migration as needed.
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