Need help loading design macro in ModelSim after generating sim model in Qsys

[Altera_Forum]

Wondering if anyone can help. Bottom line is I'm trying to load a simulation model specifically generated with Qsys into ModelSim, and all my attempts have failed. I've spent about 8 hours trying to figure this out, so I'm hoping a more experienced Quartus/ModelSim veteran can help. 

 In short, I generated a testbench system in Qsys, followed by the simulation model in Verilog. I opened ModelSim and executed the msim_setup.tcl macro and received the following error: ... # ** Error: (vlog-7) Failed to open design unit file "./..//submodules/verbosity_pkg.sv" in read mode. # C:/intelFPGA/16.1/modelsim_ase/win32aloem/vlog failed. # No such file or directory. (errno = ENOENT) ... # Load canceled # Load canceled  The next post here shows my complete steps, but anything I do after this point seems not to work. I tried loading all kinds of files to no avail. Am I missing an important step? I went through a few of the manuals and still have no luck.

[Altera_Forum]

Here are the steps I took: 

 1) I generated a testbench in Qsys with Generate>Generate Testbench System.  2) I then generated my HDL with Generate>Generate HDL>"Create simulation model == Verilog". This produces a folder {project directory}/{system fileneame}/simulation/ 3) In modelsim, I created a new project, added the toplevel file in the /simulaton/ folder 4) In modelsim, I tried File>Load>Marco File>{./simulation/mentor/msim_setup.tcl} 5) Nothing happens, so I run dev_com and com. 6) Recieve error:  # ** Error: (vlog-7) Failed to open design unit file "./..//submodules/verbosity_pkg.sv" in read mode. # C:/intelFPGA/16.1/modelsim_ase/win32aloem/vlog failed. # Load canceled # Load canceled 7) Check for spaces in pathnames. There are none. 8) Tried to set up my own simulaton with. Simulate>Start Simulation>work>{toplevel file.v}. Also loaded all libraries that were compiled in the compile tab. The results are produced below:  # vsim -gui -Lf altera_mf_ver work.single_sys_path -L work -L altera_common_sv_packages -L avalon_st_adapter -L avalon_st_adapter_001 -L c2 -L clock_mod -L clock_source -L demux -L discard_sink -L error_adapter_0 -L fe -L final_buff_ovf -L ip6_buff_ovf -L mt6d_process_path -L mt6d_srt -L mux -L pa -L packet_gen -L reset_source -L srt_dp_bwc  # Start time: 18:55:49 on Mar 02,2017 # Loading work.single_sys_path # ** Error: (vsim-3033) C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/single_sys_path.v(55): Instantiation of 'clock_mod' failed. The design unit was not found. # Time: 0 ps Iteration: 0 Instance: /single_sys_path File: C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/single_sys_path.v # Searched libraries: # C:/intelFPGA/16.1/modelsim_ase/altera/verilog/altera_mf # C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/libraries/work # C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/libraries/altera_common_sv_packages # C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/libraries/avalon_st_adapter # C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/libraries/avalon_st_adapter_001 # C:/Users/Joseph/Documents/local_repos/he_mt6d/single_sys_path/simulation/libraries/c2 {continues to list all libraries.} ... and basically for every module thereafter repeats this error