Need to feed two buses with one output

[Altera_Forum]

Hello everybody, 

 In my top level design in Quartus I am trying to feed the LSB of two buses with a signal which comes out of a block, usually I do this by naming the output signal the same name as the LSB of the bus:  lv_to_uc_status_i[0]  But I cannot name the output signal twice, so how can I tell Quartus that I need to feed two buses with this signal ?  Thanks, Eric

[Altera_Forum]

--- Quote Start ---  Hello everybody,  In my top level design in Quartus I am trying to feed the LSB of two buses with a signal which comes out of a block, usually I do this by naming the output signal the same name as the LSB of the bus:  lv_to_uc_status_i[0]  But I cannot name the output signal twice, so how can I tell Quartus that I need to feed two buses with this signal ?  Thanks, Eric  --- Quote End ---    Hi Eric,  what are you using Verilog, VHDL schematics  Kind regards  GPK

[Altera_Forum]

Hello Pletz, 

 Thanks for your answer ! I am using Schematics, in Verilog this is pretty easy actually, turns out this is also pretty easy in schematics. I need to feed the signal into  2 wire buffers, on the other side of these buffers I can feed two inputs  in the top level. See the Snagit picture I have attached below.  Again, thanks for your answer !!  Cheers, Eric