- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello everybody,
In my top level design in Quartus I am trying to feed the LSB of two buses with a signal which comes out of a block, usually I do this by naming the output signal the same name as the LSB of the bus: lv_to_uc_status_i[0] But I cannot name the output signal twice, so how can I tell Quartus that I need to feed two buses with this signal ? Thanks, EricLink Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Hello everybody, In my top level design in Quartus I am trying to feed the LSB of two buses with a signal which comes out of a block, usually I do this by naming the output signal the same name as the LSB of the bus: lv_to_uc_status_i[0] But I cannot name the output signal twice, so how can I tell Quartus that I need to feed two buses with this signal ? Thanks, Eric --- Quote End --- Hi Eric, what are you using Verilog, VHDL schematics Kind regards GPK
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Pletz,
Thanks for your answer ! I am using Schematics, in Verilog this is pretty easy actually, turns out this is also pretty easy in schematics. I need to feed the signal into 2 wire buffers, on the other side of these buffers I can feed two inputs in the top level. See the Snagit picture I have attached below. Again, thanks for your answer !! Cheers, Eric![](/skins/images/318B71AC6E18CAB8E2CA944B2397E849/responsive_peak/images/icon_anonymous_message.png)
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page