New to OpenCL help

[Altera_Forum]

Hi, 

 I am completely new to OpenCL for FPGAs.  My understanding previously was that OpenCL is a software framework for writing code that can execute across different CPUs and GPUs.  In order to use OpenCL for an FPGA, do I need to have a GPU or CPU image developed in HDL loaded on it first?  I'm confused as to how it would work in that one could just develop OpenCL C code, compile it and load it onto the FPGA.  Many thanks in advance.

[Altera_Forum]

No, you do not need to have a GPU/CPU image or anything else on your FPGA. 

 The Altera OpenCL SDK compiler takes your OpenCL program and compiles it to hardware description language in Verilog. This Verilog code is then compiled to FPGA programming file using Altera's standard tools. The SDK also provides libraries for automatically programming the FPGA with this programming file, as well as for communicating with the host CPU.   The whole process is not different than how you would run the same OpenCL program on the CPU or on an GPU.    --- Quote Start ---  Hi,  I am completely new to OpenCL for FPGAs.  My understanding previously was that OpenCL is a software framework for writing code that can execute across different CPUs and GPUs.  In order to use OpenCL for an FPGA, do I need to have a GPU or CPU image developed in HDL loaded on it first?  I'm confused as to how it would work in that one could just develop OpenCL C code, compile it and load it onto the FPGA.  Many thanks in advance.  --- Quote End ---  

[Altera_Forum]

So is it possible to do complete development of hardware in the FPGA without writing any HDL? Can IP cores such as a PCIe core be developed from OpenCL? 

 I have downloaded a "hello world" OpenCL generated rbf image from the Bittware website. It seems that this already has some PCIe core as it is detected over PCIe when I start the host. Would this image of been generated completely using OpenCL or with a combination of Altera's IP cores for use in Qsys etc. ?  Thanks for the info.

[Altera_Forum]

The AOC compiler automatically generate HDL codes based on you OpenCL kernel written in C. Then Qsys/Quatrus will compile them with vendor provided PCIe core and memory controller. So yes, you don't need to write any HDL to develop OpenCL kernels.

[Altera_Forum]

--- Quote Start ---  So is it possible to do complete development of hardware in the FPGA without writing any HDL? Can IP cores such as a PCIe core be developed from OpenCL?  I have downloaded a "hello world" OpenCL generated rbf image from the Bittware website. It seems that this already has some PCIe core as it is detected over PCIe when I start the host. Would this image of been generated completely using OpenCL or with a combination of Altera's IP cores for use in Qsys etc. ?  Thanks for the info.  --- Quote End ---    You can look at the designs examples on the Altera's OpenCL page. The programmer only develops the OpenCL program (.cl) that does the computation and the host program that launches this OpenCL program. All the communication between the host and the FPGA is automatically handled by the tool. You do not need to write a single line of Verilog/etc.

[Altera_Forum]

There is also one huge difference between compiling openCL for a GPU and for an FPGA. It takes the compiler several hours to build the hardware image that gets loaded onto the FPGA, so compilation is not a trivial process. Loading onto the board itself is pretty fast.