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jrothlander
Beginner
297 Views

Newbie: Logic gates are inverted once deployed to board

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I'm new to FPGAs and just got Quartus installed and a dev board setup for the first time. 

For my first test, I setup a schematic with a single two input AND gate. This is my hello world project attempt, just to see if everything is working. The two inputs to the AND gate are switches on the board and the output is a built-in LED. It works, but it's inverted. But it is not set to invert. What am I missing?

If both switches are high, the AND is low, if either switch is low, the AND is high. Seems inverted. Any idea why that would be? The properties on the AND gate do say that both the input and output inversion = false. So I don't see why the logic is inverted. I'm missing something here.

Could it be that the LED display is using common GND vs common VCC? What about the I/O Standard setting? How do you know what that needs to be?

Any help/suggestions are much appreciated. 

Best regards,

Jon Rothlander

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ak6dn
Valued Contributor II
266 Views

Many LED driver setups on development boards drive the LED active low, meaning you need to drive the output LOW to turn the LED ON, so a logic 1 is LED OFF, and a logic 0 is LED ON (ie, 'inverted' logic).

This is done because many (older, for the most part) FPGA outputs can sink a lot more current than they can source for driving a LED. Not so true any more with symmetrical high drive CMOS outputs, or usage of LEDs that are very efficient (ie, only require 2ma to light it up).

So the bottom line is you have to look at the schematic of your board to see how the LEDs are driven.

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5 Replies
jrothlander
Beginner
284 Views

Yeah, that seems to be the issue... I used a 7 segment LED that is either common anode or cathode, which changes the logic on me. When I flipped it to use a standard LED, it works fine. Guess I need to test the 7-segment LEDS a bit and see exactly what they are, before I try to use them. 

ak6dn
Valued Contributor II
267 Views

Many LED driver setups on development boards drive the LED active low, meaning you need to drive the output LOW to turn the LED ON, so a logic 1 is LED OFF, and a logic 0 is LED ON (ie, 'inverted' logic).

This is done because many (older, for the most part) FPGA outputs can sink a lot more current than they can source for driving a LED. Not so true any more with symmetrical high drive CMOS outputs, or usage of LEDs that are very efficient (ie, only require 2ma to light it up).

So the bottom line is you have to look at the schematic of your board to see how the LEDs are driven.

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jrothlander
Beginner
241 Views

Thanks for your reply. Your post made me look at the issue correctly and realize what was wrong.

Unfortunately, I have not been able to find a schematic of the DE0 board. I suspect Terasic doesn't publish it. They don't show it in the datasheet nor is it available from their website. But they do mention in the manual that high turns on the LED segments. So I was able to verify that after you mentioned they might be on when low. So similar to what you were saying, I had them reversed. 

I had them reversed because I originally started out by approaching the display by turning everything segment on, then logically turning off the ones that are not needed. So for say an 8, I turn all of the LEDs on, then turn off segment g. Versus turning on 7 segments, I only turn off the 1. Logically, I think it works out to less gates, less complexity. But in the end, it was confusing and I flipped it to turn on the ones I need, but left the inverted logic setup.

Of course, hardcoding this in 12 lines of Verilog or VHDL is the way to go. I was just working through this as a learning exercise.  Thanks for your help.

Best regards,

Jon Rothlander

SyafieqS_Intel
Moderator
275 Views

Hi Jon,


Have you simulate your and gate? Is it behave as expected? Where both input "HIGH" output is "HIGH"? 


Thanks,

Regards


jrothlander
Beginner
272 Views

Good point. I have not figure out how to run a simulation yet. I did try to run the simulation, but it fails to start. So I'll focus on getting that worked out.

Thanks for the suggestion.

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