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Valued Contributor III
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Newbie Verilog question

Hi all, 

 

I have an 18 bit signed register ( reg signed [17:0] acc; ) but wish to only bring the top 8 bits out of the module for (read only) access elsewhere. 

 

Can I can use a wire type since the data does not need to be further processed ? 

 

Also, how do I make the assignment ? 

 

 

Are there any more appripriate forums for these type of questions ? 

 

Thanks, 

 

Mark
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