No timing path applicable to specified source and destination

[Altera_Forum]

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus II 7.1 : 

 From To Assignment Name Value Enabled  CLK_OUT_48 N_SLWR th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[0] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[1] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[2] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[3] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[4] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[5] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[6] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[7] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[8] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[9] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[10] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[11] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[12] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[13] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[14] th Requirement 4 ns Yes CLK_OUT_48 DATA_OUT[15] th Requirement 4 ns Yes  The nodes were taken from the Node Finder and i have tried both the "post fitting" and "pins" filters. Regardless how i specify the source/destination i end up with the following in the compilation report (under "Ignored Timing Assignments"):  th Requirement 5 ns CLK_OUT_48 DATA_OUT[0] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[10] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[11] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[12] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[13] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[14] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[15] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[1] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[2] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[3] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[4] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[5] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[6] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[7] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[8] No timing path applicable to specified source and destination th Requirement 5 ns CLK_OUT_48 DATA_OUT[9] No timing path applicable to specified source and destination th Requirement 4 ns CLK_OUT_48 N_SLWR No timing path applicable to specified source and destination tsu Requirement 4 ns * CLK_OUT_60 No timing path applicable to specified source and destination  Any help is appreciated.

[Altera_Forum]

The said constraint could be achieved with Output_Minimum_Delay (data) respectivly Output_Maxmum_Delay (clock) assignments, hold_time anysis is related to internal registers only.  

 Before defining any constraints in detail, you should consider which timing could be expected normally respectively how to conncted the logic to achieve an intended timing relation. E. g. if clock output is connected to a global clock and data sourced from registers clocked with the same clock, you could expect the intended timing as normal behaviour.

[Altera_Forum]

If you're doing device-centric constraints(like Tsu and Th on the input ports), then on the output side you want to use Tco and Min Tco constraints. Most user's just apply Tco and Min Tco directly to the port(in the To column, as all single-point assignments are there), and leave it at that. (And as always look at TimeQuest when you get a chance...)

[Altera_Forum]

--- Quote Start ---  The said constraint could be achieved with Output_Minimum_Delay (data) respectivly Output_Maxmum_Delay (clock) assignments, hold_time anysis is related to internal registers only.   Before defining any constraints in detail, you should consider which timing could be expected normally respectively how to conncted the logic to achieve an intended timing relation. E. g. if clock output is connected to a global clock and data sourced from registers clocked with the same clock, you could expect the intended timing as normal behaviour.  --- Quote End ---    I don't understand why i can't specify a certain hold time on the output registers in the FPGA. In this case, i'm using the LAI to look at the output signals so i want the correct setup and hold times to be existent not only at the actual external output signals but also on the corresponding LAI signals.  I tried to assign setup and hold times to the data path earlier inside the FPGA but the result is the same; the assignments are ignored by Quartus II.  I will look at the output max/min delay settings too.  Thanks.

[Altera_Forum]

--- Quote Start ---  If you're doing device-centric constraints(like Tsu and Th on the input ports), then on the output side you want to use Tco and Min Tco constraints. Most user's just apply Tco and Min Tco directly to the port(in the To column, as all single-point assignments are there), and leave it at that. (And as always look at TimeQuest when you get a chance...)  --- Quote End ---    But i want to specify a certain Tsu and Th on the OUTPUT port, not on the input port. I.e. i want to ensure that my external FIFO i'm writing data generated by the FPGA has the correct setup and hold times (required around 5 ns while now only 1ns). Tco should only specify the time data is earliest *available* after clk, not Th...?  I hope i'll get the hang of this soon, i'm still a newbie...

[Altera_Forum]

I'm not sure what you mean about why can't you specify an external hold time? Hold time defines a relationship between the clock and data arriving at a register. Since you're sending data off chip, the hold time would technically be applied to the downstream register, off chip. This is what external assignments do, basically describe an external register and what it's timing is. But if you want to describe things in terms of the FPGA, Tco and Min Tco are what you want. Bottom line is hold isn't meant to work on output pins, but the other two types of assignments are and should be used. Good luck.

[Altera_Forum]

--- Quote Start ---  Hold time defines a relationship between the clock and data arriving at a register.  --- Quote End ---    Does it? Doesn't it define the time between the clock edge and the point in time the data is *removed* from the destination register's input? I.e. the time the data must be stable after the clock such that the receiving register will have enough time to latch the data. The setup time would be the time between the data is valid and the clock edge that acts on the data. This what confuses me.   Since i want to (first) make sure that my internal signals have a 5 ns hold time i should be able to specify in the assignment editor that Th between the clock and a certain data signal should be 4ns. Or perhaps Quartus tries to be smart and *removes* the hold time on internal nodes because it knows it is not required by the internal FFs?  I also do not understand what the point is to specify a certain Th on INPUT ports since Th on an input port is defined by the external driver - no setting in Quartus will change the external device behavior. The only way i can see Th specified on an input port is if Quartus II will actually internally generate a FF to buffer the data but if this is done the data should be delayed by an additional clock cycle which is clearly not what we want.   Any clarification or pointers to decent documentation on this subject is greatly appreciated.

[Altera_Forum]

Well, i've tried to change any and all settings but i can't delay the clock signal or the data signals! I've tried Tco and min Tco as well as the maximum/minimum output delay. Any timing assignments entered in the assignment editor are flagged as invalid ("No timing path applicable to specified source and destination") and none of the output delay options actually has any effect on the output signals! 

 Any idea what could be wrong here? All i need to do is to delay the output clock by 5ns to fix the current hold problem...

[Altera_Forum]

FYI: This particular issue has been fixed by inverting the clock signal (good setup and hold could be achieved). I, however, have been completely unsuccessful in affecting the external timing of the Cyclone II using timing assignments.

[Altera_Forum]

Probably get rid of the clock name in the From column and just leave the port name in the To column. This is how I usually see it. I thought the clock name would work, but it's definitely not necessary. (If you have multiple registers driving out, then put the name of the register in the From column. I've seen this when the data and OE registers have different Tco requirements.)

[Altera_Forum]

--- Quote Start ---  Probably get rid of the clock name in the From column and just leave the port name in the To column. This is how I usually see it. I thought the clock name would work, but it's definitely not necessary. (If you have multiple registers driving out, then put the name of the register in the From column. I've seen this when the data and OE registers have different Tco requirements.)  --- Quote End ---    Whatever i do i can't move any signals even a ps... I have tried to use the "Delay from output register to output pin" assignment (both with a delay of 1 and 1000 in case the setting is in ps) but the signal is not delayed. I have tried to delay both the clock signal and the data signal. The result is the same.  Is it enough to just add timing assignments in the assignment editor? Or must the delay features in the synthesized code somehow be enabled elsewhere?  Note that i am using regular I/O pins as clock outputs on the I/O Banks - does this matter?

[Altera_Forum]

FYI: I gave up on the Quartus II timing assignments and instead inverted the clock signal and followed with four LCELLs. This resulted in my clock aligned perfectly in the middle of my data. I have around 4 ns margin in either direction so i'm 'hoping' that this will work despite variation in delay with different silicon batches...

[Altera_Forum]

The point is, that Quartus software has no means to achieve a 4 ns order of magnitude delay in place and route. The said output register to output pin delay should be utilized in timing-driven P&R automaticly, but probably you're not using output registers in your design. Comparing output and LE register usage, LE register would have generally higher tco, cause routíng delay is added. Thus it could be, that Quartus already has achieved the highest possible tco value. Some amount of output delay could be added by decreasing current strength, increasing also sensitivity to parameter variations. 

 Using a phase shifted PLL clock is the most flexible way to adjust timing, but may inappropriate for your design.

[Altera_Forum]

Thanks FvM. You are probably correct in that a 4ns programmable delay is not possible to achieve (possibly because i'm not using output registers). The LCELL approach works fine so i'll leave it at that - the clock frequency is only 120 MHz so i have lots of wiggle room before the timings break down so this should work fine.