Nodes missing in signaltap

[Altera_Forum]

Hello, 

 I've got 2 sdram controllers connected to a NIOS II system. These sdram-controllers are exactly the same (they address only different address-spaces) but when I want to display some signals in signaltap (called m_cmd[4] through m_cmd[0]) I cannot select the required signals from the first controller. The first controller has signals called: m_cmd[0]~_Duplicate_1 while the second controller has the correct signal-names called: m_cmd[0], etc. Does anybody have some idea why there is a difference between the signals of both controllers and which setting I could change to make the signals from the first controller available.  Best regards,  Wamor

[Altera_Forum]

Hi, 

are these signals identical (connected to both sdram controllers) or is there any logic in between. If the signals are identical (as the ~_Duplicate_1 would point to), why should there be two signals to tap? The compiler optimizes your code for implementation and thus also optimizes "away" theses duplicate signals. Nevermind there is an option to assign the signal as "preserve for simulation" (never really tested this) in the assignment editor...  BR

[Altera_Forum]

Hello Carl, 

 Both SDRAM-controllers are 2 complete independent controllers and have seperate hdl-files. They only use the same signal-names in both files because they are generated by QSYS. I tried to look for the "preserve for simulation" setting in the assignment editor but cannot find it. Is this also available in the Quartus web-edition? If so, can you point me to the exact screen where I can find this?  Best regards,  Wamor

[Altera_Forum]

Wamor, you can try to change the option "Filter" when you search for your signals. Like for example to "Post-synthesis".  

But maybe after synthesis some of the signals you have selected may get lost (signal name in RED), because they are not available. Usually it works, but not always.   The synthesis-tool is forced not to optimize special signals with KEEP.    --- Quote Start ---    constant debug : boolean := false; -- enable attribute for chipscope debug  attribute keep : boolean;   attribute keep of MasterTimeOutCounter : signal is debug;   --- Quote End ---  

[Altera_Forum]

Hello vhdl_world, 

 Could you point me where I can find the option "Filter" I am using verilog. Should /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" ; keep = 1 */ do the same trick with verilog? I still have signal names in RED. Is the ; the right seperator for mixing attributes?  Thank you and best regards,  Wamor

[Altera_Forum]

When you tap the node, are you using pre-synthesis registers? I think if your node is referring to register, it might most probably going to be preserve. 

So far, Signaltap works fine when I am using the pre-synthesis Signaltap register, it gives me meaningful name and does not optimized away.

[Altera_Forum]

Hi Wamor, 

 Forget about messing with those attributes. I think you are tapping post-fitting nodes unknowingly. I am guessing you are not trying to save compilation time or preserve timing by tapping post-fitting nodes. When you open nodefinder, make sure that you are selecting "Signaltap II pre-synthesis nodes". You'll find plenty of useful nodes on your controller to tap. Long while ago, nodefinder opened from SignalTap set the "Signaltap II post-fitting nodes" by default. It hides the best feature of SignalTap, IMHO. Moreover, in the most recent release, nodefinder hides that filter choice too. You have to expand it first using a button with rotated ">>".