--- Quote Start ---
Review the User Guide
designing with low-level primitives http://www.altera.com/literature/ug/ug_low_level.pdf --- Quote End ---
That's really what I need. Thank you very much.
By the way, I found this for Xilinx for OBUF (
http://www.cs.indiana.edu/hmg/le/project-home/xilinx/ise_10.1/ise/doc/usenglish/isehelp/cpld_all/libs_le_obuf.htm) which I'm new to
They say:
--- Quote Start ---
unless they already exist, copy the following two statements and paste them before the entity declaration. Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUF: Single-ended Output Buffer
-- All devices
-- Xilinx HDL Libraries Guide, version 10.1.2
OBUF_inst : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I -- Buffer input);
-- End of OBUF_inst instantiation
--- Quote End ---
But it's for Xilinx, I also found this from Altera
http://www.altera.com/literature/an/an307.pdf Could you have a quick look at this document on page 31 and 32?
I see that it talks about OBUF (and more) conversion for Quartus II. I'm not sure if they are correct for using OBUF for Altera Devicdes as I don't have many chance to test it, and I don't even know how to do that. Could you tell me if it's correct to create an OBUF to a signal in Quartus II please?
Thank you,
Tan
