Optimizer

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Optimizer

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Hi,

I (still) got some problems with my design. It is a design with a top-down structure - so I have a top-level file and several lower-level VHDL files.

When I make a new block on a lower-level schematic I try to simulate the outputs of that block, but if I haven't connected the outputs to anything the compiler optimizes part of the block away. Is it possible to prevent this from happening (adding DFF to outputs)?

Also in a process i specify some VARIABLES, but it seems that they dissapear in the node-finder in the simulator. Is it somehow possible to prevent the VARIABLES from dissapearing or should it be SIGNALS for that?

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For more complete information about compiler optimizations, see our Optimization Notice.