PCIE - pin selection for two controllers in Stratix V

[Altera_Forum]

Folks, 

 I need to implement two PCIe Gen 2 x8 controllers in Stratix V device (5SGXEA7K2F40C2). Using MegaWizard I've generated the two variants. One of them needs to be connected to the left side and the other to the right side chip pins. I tried various things: 1. In pin planner, force location as EDGE_LEFT and EDGE_RIGHT on the pins 2. In QSF file, set_location_assignment EDGE_LEFT -to <pin> None of them result in the pin assignments that I need. I am pretty sure that the chip has two Hard IP controllers. I can't seem to get the automatic assigner to pick the correct pin groups on the left edge or the right edge as needed for my use.  How can I select the serdes pins that I need?  Thanks in advance for your help.

[Altera_Forum]

EDGE_LEFT and EDGE_RIGHT are with reference to die not package. By flipping the edge assignment side (EDGE_LEFT to EDGE_RIGHT and vice-versa), I was able to get what I need.