PLL Merging

Altera_Forum · ‎01-19-2011

I have two designs very similar, both instantiate one PLL, two ALT_LVDS_TX and two ALT_LVDX_RX.

Design A, drives the output of the PLL to a pin, design B does not.

For design A, Quartus generates a design with 3 PLLs (which is what I expect, due to merging the 4 ALT_LVDS PLL into two).

For design B, Quartus generates a design with 4 PLLs, and if I output a clock from the PLL, it generates a design with 5 PLLs.

The ALT_LVDS code fro both A and B are the same.

Any ideas what's causing this behavior and what can I tale a look at to figure what what's going on.

Thanks

Altera_Forum · ‎01-20-2011

Each PLL can have only two clock inputs. If you have different clock sources, then the system will use more PLL.