PLL Reconfiguration Timing Constraint

[JLee25]

Hi,

  I have a question on the PLL timing constraint when working with Cyclone V Pll reconfiguration.

  In my case, I have the PLL output 2 different frequency, 1 is 10MHz and the other is 300MHz. Then I have to use the reconfiguration.

  Then how could I constraint the clock instead of using "derive_pll_clocks".

Thank you!

[Farabi]

Hello, 

You may want to refer to this document: https://www.intel.cn/content/dam/altera-www/global/en_US/kdb/rd10162012_514/pll_clock_switchover_constraints_in_28nm.pdf

regards,
Farabi

[Farabi]

Hello, 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,
Farabi