Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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PLL Reconfiguration Timing Constraint

JLee25
Novice
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Hi,

  I have a question on the PLL timing constraint when working with Cyclone V Pll reconfiguration.

 

  In my case, I have the PLL output 2 different frequency, 1 is 10MHz and the other is 300MHz. Then I have to use the reconfiguration.

  Then how could I constraint the clock instead of using "derive_pll_clocks".

 

Thank you!

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Farabi
Employee
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Farabi
Employee
378 Views

Hello, 

 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

regards,
Farabi

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