PLL dedicated clock outputs

[Altera_Forum]

I have got the following message. 

 Warning (15064): PLL "Std_CycloneIV:inst|cpu_pll:the_cpu_pll|cpu_pll_altpll_6nm2:sd1|pll7" output port clk[2] feeds output pin "sram_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance  This PLL is generated inside SOPC builder. The physical pin for this output clock is a dedicated PLL output pin. Even if I added the global clock assignment to this net, I still get this message. I don't know why?    Many thanks in advance for your advice.

[Altera_Forum]

Is it the dedicated clock output for the specified PLL?

[Altera_Forum]

Not too sure. I thought that Quartus-II is clever enough to automatically assign the right PLL.

[Altera_Forum]

If you've assigned the output pin, then yes, it should map the correct PLL.

[Altera_Forum]

Yes, I did assign the output of the PLL to the dedicated PLL output pin but...

[Altera_Forum]

Hello bcao, 

 i know this warning.  In your device you have 4 PLL's. One in every edge of your device. (Look into the Chip Planner). Every PLL has dedicated clock input pins and output pins. (Look into the Device Handbook). If you use one dedicated pll clock output pin to your external Memory, you must check whether the associated pll is selected by the fitter. If not, you can use the assignment editor to make a location assignment for the used pll to correct this.  See Attachmend.  In my case, after the location correction, the warning was gone.  I hope I could help

[Altera_Forum]

--- Quote Start ---  I thought that Quartus-II is clever enough to automatically assign the right PLL  --- Quote End ---   Apparently your clock input and clock ouput are not in reach of the same PLL. In this case, there's no simple "right" PLL to choose. The selection used by Quartus is probably the best one.

[Altera_Forum]

Thank you all for your suggestions. 

 Nicolas, I tried your approach as shown as follows.   Ok std_2s60ES:inst|cpu_pll:the_cpu_pll Location PLL_1 Yes   However, I have got compile error as follows.   Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|prev_reset" to location PLL_1 -- node is type Register cell Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|readdata[0]~0" to location PLL_1 -- node is type Combinational cell Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|pfdena_reg" to location PLL_1 -- node is type Register cell Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|readdata[1]~1" to location PLL_1 -- node is type Combinational cell Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|w_reset~0" to location PLL_1 -- node is type Combinational cell Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|readdata[0]~2" to location PLL_1 -- node is type Combinational cell Error (171011): Can't assign node "std_2s60ES:inst|cpu_pll:the_cpu_pll|pfdena_reg~0" to location PLL_1 -- node is type Combinational cell   FvM, what do you mean by "Apparently your clock input and clock ouput are not in reach of the same PLL"? The input pin and output pin to the PLL are the dedictaed clock input pin and clock output pin of that PLL, respectively.

[Altera_Forum]

Hello Bcao, 

 Did you find a solution to your problem? Because I am encountering the exact same issue and I have no idea what is wrong...  Thanks a lot

[Altera_Forum]

For some reason the type, name, or ID of the ATOM may have changed from pre-map to post-map. If you have them, you might try removing any Virtual I/O. If the "pin" location assignment and the virtual pin assignment are mismatched (name, ATOM, ID) you can get this error.  

 For instance you have  set_instance_assignment -name VIRTUAL_PIN ON -to *   The "*" will set all ports to virtual and create a problem in some cases. This doesn't always work if you have assigned pins.   Instead you can use the synthesis keep attribute.wire keep_wire /* synthesis keep */;