PLL megacore probs.build my own??

[Altera_Forum]

Hi all, 

 I want to implement a PLL that will lock onto & track an incoming signal of about 30KHz and output a multiple of that locked frequency. I tried using Quartus's PLL megacore function but it wont accept a 30KHz input signal, saying that its too low. Is there something I might be doing wrong or do I have to design my own PLL using the an XOR,NCO & the FIR filter megacores(if thats even possible)???

[Altera_Forum]

Looking at the PLL hardware specification clarifies, that it can't use a 30 kHz reference clock. Without going too deep into details, it's simply impossible for a PLL with a 0.5 to 1 GHZ VCO range. 

 Designing "your own" PLL is actually an option. But an low frequency equivalent to the FPGA PLL would be rather a basic all digtal PLL than a NCO design dealing with digitized waveform. Although the latter is also feasible, of course.

[Altera_Forum]

I understand. My knowledge of PLL's though goes as far as analogue(hence the mention of the analogue equivalent subsystems like NCO & filter etc.). 

 How does the "basic" DPLL you mentioned differ from the, now seemingly labourous usage of NCO's & such? Another reason I mentioned an NCO is that I was advised (by a microelectronics lover,hence analogue again)that a VCO can output a multiplied version of the locked frequency,which is what I need to do.

[Altera_Forum]

A DPLL can also use a VCO equivalent operating at multiple of the reference input, but as the VCO is time-discrete, it's clock edges are coinciding with the system clock events, a higher VCO frequency means more jitter in the output signal. But a NCO is time-discrete as well.

[Altera_Forum]

Hi, 

You may wish to consider the 4046 http://www.standardics.nxp.com/products/plls/4046/   Regards

[Altera_Forum]

Hi again people. 

 Thank you for your replies. I struggled the whole of today to implement the PLL in Quartus but I couldnt get it right. one of my problems was that I have no control over the output bit width of some of the megacores (like te filter). The NCO also determines the input bit width according to my specs & this causes there to be a mismatch between the subsystems.  Would the NCO be able to output a 5MHz & 20MHz singal from a locked 31,250KHz signal anyway?

[Altera_Forum]

If these are separate NCO output signals, they won't be phase locked, I think. The design is obviously different from a classical PLL, where the VCO output is divided down and phase locked to the reference input. 

 I'm not clear about the specific implementation problems you reported. I never used a Megacore to implement a PLL, but this should work as well.

[Altera_Forum]

I am trying to implement a classic PLL actually; I've just never done it in software before. What I basically need to do is lock onto an incoming 31.250KHz Signal with the PLL. The outputs should be 2 frequncies, one at 5MHz (incoming times 160) and the other should be 20MHz. Whats the simplest way to achieve this? (this is my challenge in a nutshell)

[Altera_Forum]

I have a rough idea about what you're intending, but not in all details. Particularly: 

- What's the reference waveform? - What are the requirements for the 5 and 20 MHz signals? (Waveform, acceptable phase jitter, phase locking needed) - Dynamic parameters of reference signal (frequency tolerance, jitter) - Required lock time

[Altera_Forum]

The incoming signal to be locked onto is a correlator output. Basically two siganls are correlated and the output is a signal with periodic peaks where the two signals are the same. I need to lock onto the frequency of those peaks and multiply that frequency with 160 in order to sample. 

Its a frame and symbol synchronisation opearation, where the frames are at the 31.250KHz frequency & the symbols at 5MHz.   the output frequencies are therefore clocks with 50% duty ratio & the lock in time/settling time can be anything (obviously, the quiker the acquisition the better, so tradeoffs will have to be made between the settling time and the allowable noise/jitter). The noise/jitter,therefore is not particularly specified.

[Altera_Forum]

--- Quote Start ---  The noise/jitter,therefore is not particularly specified.  --- Quote End ---  To mention an obvious fact. Above a certain input signal jitter, no meaningful PLL operation can be expected. A phase noise analysis of the input signal can answer the question.  Generally, I hear from your answer, that a time discrete 5 MHz clock based .e.g. on a 40 or 80 MHz system clock can be acceptable. This would basically allow an all-digital PLL solution.

[Altera_Forum]

Hi again. 

 I took a bit of a break from my design,but Im back at it. I've figured out how to operate the NCO for my application (using it in "frequency modulation" mode). I can set the nominal frequency by giving it a certain integer constant(equations are given) and all it needs is an input from the loop filter. FvM, you mentioned some time ago that the NCO route is more labour intensive due to the NCO's digitized waveform output and that an "all digital PLL" solution would bee easier. Whats the difference between the two?

[Altera_Forum]

If I understand right, you only need the phase accumulator from the NCO to build your PLL.

[Altera_Forum]

But the phase accumulator is given by the megafunction or can alternatively be calculated using the given equations in the user guide. This phase accumulator is then an input to the NCO in order to generate a sinusoid at my required frequency. This output sinusoid (well actually what I need is a clock, but I can hardlimit the sinusoid to get that) is what phase detector (XOR) needs, right?

[Altera_Forum]

You can use the phase accumulators most significant bit as digital clock :) 

 P.S.: Or more appropriate for a synchronous design, generate a clock enable on it's rising edge for one input clock cycle.

[Altera_Forum]

The phase accumulator cannot be read, its an input (something I have to give the NCO in order for it to output the frequency I desire). I cant therefore read its MSB...or is tere something Im still not getting?  

And thank you for your patience with me. Im really trying.

[Altera_Forum]

I'm not talking of a praticular NCO IP. A phase accumulator is simply a register. 

if rising_edge(clk) then phase <= phase + phase_increment; end if;

[Altera_Forum]

...but you mentioned earlier that I need the phase accumulator from my NCO to build my pll  

("if i understand right, you only need the phase accumulator from the nco to build your pll.").   As part of the pll, what would the input be for phase accumulator youre talking about? what I mean is that the NCO gets its input from the loop filter and adjusts its output simusoid accordingly & the that output goes back into the phase detector, who's output in turn goes into the loop filter ect.. So what Im asking is where in the pll does the phase accumulator you mention fit in?

[Altera_Forum]

Yes, there's a misunderstanding. 

  --- Quote Start ---  you only need the phase accumulator from the NCO  --- Quote End ---   I didn't mean, that you must necessarily use this phase accumulator (from the Altera NCO core). You can use any phase accumulator. I didn't think about the fact, that the Altera NCO doesn't have an output from the phase accumulator. If you're not familiar with NCO internals, you can see from the NCO MegaCore User Guide's functional description, that the phase accumulator isn't but a register and an adder. The more complex part of the NCO follows, but it's not needed for a pure digital PLL.

[Altera_Forum]

Does a pure ditital pll still need a low pass filter? I cant seem to acquire lock with the pll I've constructed Im not sure why since all the connections make sense. the XOR output gives basically peaks or 1's when there is a difference between the incoming clock and the output of my hardlimiter (i havent implemented the phase accumulator suggestion yet). The thing with this is that even if the two XOR inputs have the same frequency, if theyre not in phase there will be a train of 1's at the XOR output, which (at the moment) I put through a low pass filter (BW = 34KHz) and the output of that I input into the frequency modulator input of the NCO.  

Do I have the wrong configuration perhaps? Another thing I've tried is inputting the LPF output into the PHASE modulator input of the NCO, hoping for a phse shift to allign the two clocks so that the XOR output would eventually die out to zero. This also failed. Im not sure where to go from here.

[Altera_Forum]

--- Quote Start ---  The thing with this is that even if the two XOR inputs have the same frequency, if theyre not in phase there will be a train of 1's at the XOR output.  --- Quote End ---  Yes, a PLL has the purpose to pull the (divided) VCO phase to the input phase. With an XOR gate, both inputs must have 50% duty cycle and it operates with 90° pahse shifz between both inputs. Other phase comparator typed are achieving 0° phase shift.