Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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POWER_UP_LEVEL for Partial Reconfiguration

DNLDNL
Novice
1,901 Views

Hi.

I use dcfifo ip core which has POWER_UP_LEVEL assisment for some  registers. Quartus shows warnings:

Critical Warning(19519): The instance assignment "POWER_UP_LEVEL" on register "...|rx_fifo|auto_generated|wrptr_g1p|counter8a0", in reconfigurable partition "......", is ignored. Initial condition is not guaranteed during partial reconfiguration.

How should I handle this situation?

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sstrell
Honored Contributor III
1,889 Views

The built-in help says to simply remove the assignments:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/wqhd_power_up_level_assignment_used_in_pr_partition.htm

Are you saying the IP added these assignments when you added it to your design?  It seems like you can safely ignore this unless you have requirements for these registers after you perform a PR.

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DNLDNL
Novice
1,878 Views

This registers are part of FIFO Intel® FPGA IP(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf)

Therefore I can't remove the assignments.

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EngWei_O_Intel
Employee
1,847 Views

Can you check if you could remove those assignment in Assignment Editor? Else if the warning will goes away if you edit the generated files which isn't the best suggestion?

 

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DNLDNL
Novice
1,842 Views

I can't remove is in Assignment Editor. Can I just ignore it?

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EngWei_O_Intel
Employee
1,755 Views

I am transitioning this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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