Passed "Design Analysis" stage but failed with "Analysis & Synthesis" stage

[jeffshh056]

Hi There,

I am using Quartus 22.3/22.4 version to compile my design. 

My design contains many folders and many source code,  including *.svh files.

I am using quartus_sh to run a tcl file to do the compile.

I have added SERACH_PATH and Source code in the tcl file,  I can even pass the "Design Analysis" stage with no errors.  If my understanding is correct,  this at least shows I have include all the files.

However,  I got a bunch of "Can't elaborate user hierarchy ***" errors in the "Analysis & Synthesis" stage. Can someone give me some suggestion what I am missing?  Does the compile file list order matter?  I am sure I did not miss any files otherwise I cannot pass the quick-elab check.

Any suggestions?

Thank you so much!

-Shu

[ShengN_Intel]

Hi,

I don't think the compile file list order matter. In gui, may be you can go to Project -> Generate Tcl File for Project. Then in auto-generated tcl script add two lines below:

package require ::quartus::flow

...

execute_flow -compile

After running auto-generated tcl script, if there's no error then probably there's some problems with your tcl script so can do the comparison. If there's error with auto-generated tcl script as well, then probably the problem is in the design files.

Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

[jeffshh056]

Hi Sheng,

My teammate who is using Quartus in GUI mode and got the same issue.

I am using quartus_sh,  and I have package require ::quartus::flow  in my TCL file. The flow actually runs but errors out.

Info: Run task: IP Generation  (pass)

Info: Run task: Design Analysis(pass)

Info: Run task: Logic Generation(pass)

Info: Run task: Analysis & Synthesis(51 errors)

Error (16045): Instance "u_axi_bridge" instantiates undefined entity "axi_bridge" File: #######/src/xyz_ctl.sv Line: 2328
Error (16185): Can't elaborate user hierarchy "u_axi_bridge" File: ######/src/xyz_ctl.sv Line: 2328

What puzzles me is that

• I do see the design "axi_bridge" gets compiled,   I don't see compile error related to that module, why it can't elaborate?  

I am attaching the syn.elab log file here,  can you help take a look?

Thanks,

-Shu

[ShengN_Intel]

Hi Shu,

I think that's not the problem of tcl script then. Check in the axi_bridge.sv, make sure the module name is the same matched name axi_bridge. Same goes for the rest of undefine entity.

Thanks,

Best regards,

Sheng

[jeffshh056]

One more observation,  if I change to "MFCU" mode,  the synth do starts!!!

      set_global_assignment -name VERILOG_CU_MODE MFCU

Do you happen to know why it make such difference,  does it have anything to do with AUTO-DISCOVERY?

[ShengN_Intel]

Hi Shu,

Check this link https://www.intel.com/content/www/us/en/docs/programmable/683463/22-4/verify-verilog-compilation-unit.html

Actually Quartus Pro Edition use Single-file compilation unit (SFCU) method to select compilation unit files which is better method compared to Multi-file compilation unit (MFCU) method.

I don't think that would be the root cause. It's better to check whether the module name match or not.

Thanks,

BRs,

Sheng

[ShengN_Intel]

Hi Shu,

Any further update or concern?

Does your problem being resolved?