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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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15319 Discussions

Path Violation in timing analyzer

m_kumar
New Contributor I
148 Views

Hi ,

Iam working max10 fpga , in timing analyzer i'm getting path violations can i get any help to solve this problem.

Report Timing: Found 200 setup paths (200 violated). Worst case slack is -0.575

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3 Replies
sstrell
Honored Contributor III
135 Views

Without seeing your design and a .sdc file, there's really no way to help with this.  More details needed.

SyafieqS
Moderator
131 Views

Hi Manoj,


Maybe some information (sdc, timing report) to evaluate the issue here needed


m_kumar
New Contributor I
127 Views

Hi sir thanks for the reply i reached the desired timing . Problem was in my sdc file timing  values.

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