Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform designer error : subsystem ava mm bridge slave port

CAlex
New Contributor II
1,796 Views

Hi,

Ive made a subsystem into my main system:

CAlex_0-1705655077302.png

 

here is my sub system:

CAlex_1-1705655120073.png

 

The error is :

Error: soc_system.subsystem_0.mm_bridge_0_s0: Interface must have an associated clock

 

Reguards

Alex

 

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1 Solution
ShengN_Intel
Employee
1,576 Views

Hi,

 

At Component Editor Signals & Interfaces tab, add Clock Output and Reset Output signals check screenshot below:

Screenshot 2024-01-23 170434.png

Then modify the Clock Output and Reset Output Signals setting like below screenshot:

Screenshot 2024-01-23 170606.pngScreenshot 2024-01-23 170815.png

 

Thanks,

Best Regards,

Sheng

 

View solution in original post

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sstrell
Honored Contributor III
1,772 Views

The exported interface names for clock and reset in the second image do not seem to match the clock and reset interface names of the subsystem in the first image.  I'm not sure why the names are different, but it might just require a refresh or edit and save of the subsystem to correct.

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CAlex
New Contributor II
1,760 Views

Hi

you are right for the name error and is solved,

the main error still exist though,

 

Thank you for the help by the way

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ShengN_Intel
Employee
1,711 Views

Hi,

 

Check the Clock tab, is that the Avalon-MM Pipeline Bridge Clock Input being connected correctly?

I'll encounter the same problem when Clock Input is not connected check screenshot below:

ShengN_Intel_0-1705894469124.pngShengN_Intel_1-1705894554596.png

If the problem still persist even the Clock Input is connected properly, then probably try to replace with a new Avalon-MM Pipeline Bridge IP and see.

 

Thanks,

Regards,

Sheng

 

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CAlex
New Contributor II
1,697 Views

HI

The problem still exist, the clk is connected properly:

CAlex_0-1705903503353.png

 

CAlex_1-1705903549876.png

 

Reguards

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ShengN_Intel
Employee
1,686 Views

Hi,


The Custom Reset Synchronizer is your custom IP? If replace Custom Reset Synchronizer with Clock Source Intel IP any difference?

If no more error means the problem at the Custom Reset Synchronizer.


Thanks,

Sheng


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CAlex
New Contributor II
1,682 Views

Hi

yes you are right, the sync reset block is the problem of the issue,

but it was not my IP, it is combined with the GHRD of CycloneVsoc.

 

What this IP do to the clk is

 

```

assign clk_out = clk_in;

```

 

I dont understand why it will return such a error for my system.

 

Reguard

Alex

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sstrell
Honored Contributor III
1,643 Views

I think the issue is that with a pipeline bridge in a subsystem like this, you need to export both the agent interface (s0) and the clock interface of the bridge itself instead of going through the clock source component ("Custom Reset Synchronizer"?).

You say this is straight from the GHRD without any alterations?  Try using a standard clock source component (or Clock Bridge component if this is Pro) instead of the "Custom Reset Synchronizer" which I've never seen before.

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CAlex
New Contributor II
1,617 Views

Hi

thank you for the reply,

 

the clock source IP works just fine,

the custom reset synchronizer is from GHRD of CycloneVsoc root/ip/custom_reset_synchronizer.

 

From the other Intel example (FPGA to SDRAM example mentioned in UG), the subsystem used the same way to connect and with no warning or error.

 

So I believe I must have not set it right.

 

Reguards

Alex

 

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ShengN_Intel
Employee
1,636 Views

Hi,


Possible to provide that custom ip for taking a look?


Thanks,

Sheng


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CAlex
New Contributor II
1,618 Views

Sure,

file is attached

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ShengN_Intel
Employee
1,577 Views

Hi,

 

At Component Editor Signals & Interfaces tab, add Clock Output and Reset Output signals check screenshot below:

Screenshot 2024-01-23 170434.png

Then modify the Clock Output and Reset Output Signals setting like below screenshot:

Screenshot 2024-01-23 170606.pngScreenshot 2024-01-23 170815.png

 

Thanks,

Best Regards,

Sheng

 

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CAlex
New Contributor II
1,571 Views

Hi,

Sorry the Screen shorts are missing,

could you reload them?

 

Reguards

Alex

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CAlex
New Contributor II
1,569 Views

it's the internet issue,please ignore

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CAlex
New Contributor II
1,557 Views

HI

It is working!

very thank you for the help

 

But there is a warning said associated reset sink not detected.

 

Here is my IP setting for reset_out:

CAlex_0-1706003045184.png

Here is my sub_system:

CAlex_1-1706003091539.png

If that is not critical, then I'll ignore that.

 

Reguards

Alex

 

 

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ShengN_Intel
Employee
1,569 Views

Done uploaded. Check previous post.


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ShengN_Intel
Employee
1,476 Views

Hi,


The reset sink is the Reset Input. You may in Associated reset sinks put reset and then click finish. Then the warning will gone.


Thanks,

Best Regards,

Sheng


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CAlex
New Contributor II
1,452 Views
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