Platform designer error : subsystem ava mm bridge slave port

[CAlex]

Hi,

Ive made a subsystem into my main system:

here is my sub system:

The error is :

Error: soc_system.subsystem_0.mm_bridge_0_s0: Interface must have an associated clock

Reguards

Alex

[sstrell]

The exported interface names for clock and reset in the second image do not seem to match the clock and reset interface names of the subsystem in the first image.  I'm not sure why the names are different, but it might just require a refresh or edit and save of the subsystem to correct.

[CAlex]

Hi

you are right for the name error and is solved,

the main error still exist though,

Thank you for the help by the way

[ShengN_Intel]

Hi,

Check the Clock tab, is that the Avalon-MM Pipeline Bridge Clock Input being connected correctly?

I'll encounter the same problem when Clock Input is not connected check screenshot below:

If the problem still persist even the Clock Input is connected properly, then probably try to replace with a new Avalon-MM Pipeline Bridge IP and see.

Thanks,

Regards,

Sheng

[CAlex]

HI

The problem still exist, the clk is connected properly:

Reguards

[ShengN_Intel]

Hi,

The Custom Reset Synchronizer is your custom IP? If replace Custom Reset Synchronizer with Clock Source Intel IP any difference?

If no more error means the problem at the Custom Reset Synchronizer.

Thanks,

Sheng

[CAlex]

Hi

yes you are right, the sync reset block is the problem of the issue,

but it was not my IP, it is combined with the GHRD of CycloneVsoc.

What this IP do to the clk is

```

assign clk_out = clk_in;

```

I dont understand why it will return such a error for my system.

Reguard

Alex

[sstrell]

I think the issue is that with a pipeline bridge in a subsystem like this, you need to export both the agent interface (s0) and the clock interface of the bridge itself instead of going through the clock source component ("Custom Reset Synchronizer"?).

You say this is straight from the GHRD without any alterations?  Try using a standard clock source component (or Clock Bridge component if this is Pro) instead of the "Custom Reset Synchronizer" which I've never seen before.

[CAlex]

Hi

thank you for the reply,

the clock source IP works just fine,

the custom reset synchronizer is from GHRD of CycloneVsoc root/ip/custom_reset_synchronizer.

From the other Intel example (FPGA to SDRAM example mentioned in UG), the subsystem used the same way to connect and with no warning or error.

So I believe I must have not set it right.

Reguards

Alex

[ShengN_Intel]

Hi,

Possible to provide that custom ip for taking a look?

Thanks,

Sheng

[CAlex]

Sure,

file is attached

[ShengN_Intel · Accepted solution]

Hi,

At Component Editor Signals & Interfaces tab, add Clock Output and Reset Output signals check screenshot below:

Then modify the Clock Output and Reset Output Signals setting like below screenshot:

Thanks,

Best Regards,

Sheng

[CAlex]

Hi,

Sorry the Screen shorts are missing,

could you reload them?

Reguards

Alex

[CAlex]

it's the internet issue,please ignore

[CAlex]

HI

It is working!

very thank you for the help

But there is a warning said associated reset sink not detected.

Here is my IP setting for reset_out:

Here is my sub_system:

If that is not critical, then I'll ignore that.

Reguards

Alex

[ShengN_Intel]

Done uploaded. Check previous post.

[ShengN_Intel]

Hi,

The reset sink is the Reset Input. You may in Associated reset sinks put reset and then click finish. Then the warning will gone.

Thanks,

Best Regards,

Sheng

[CAlex]

It is solved ,thank you