Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform designer generates faulty interconnect addressing unless I use Assign Base Addresses. I don't want to use it since Addresses changes for every change in the design.

MMavi
Novice
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Hi,

I use Quartus Prime 17.1 Standard Edition. Currently, I work on a project with arria10SoC FPGA. In the project, I use Platform designer to connect some custom blocks to HPS via LWB. There are 6 different slaves currently and when I assign their addresses manually system fails. When I checked the AMM signals to a slave with SignalTapLogicAnalyser, I saw that some addresses are not accessible. I even tried to connect a JTAG to avalon master and checked the accessibility of the addresses but it didn't work either. For now, I just use assign base addresses and have to change the address maps of the code running on HPS.

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sstrell
Honored Contributor III
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You can click the little lock icon in the Base Address column in Platform Designer to prevent assigned addresses from getting changed when you use the "Assign Base Addresses" command.

 

As for the manual addresses you are trying to assign, slaves connected to the lightweight bridge are assigned to a specific area of the address map of the processor. Perhaps the addresses you are assigning are not in that area which is why it is failing.

 

#iwork4intel

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Ahmed_H_Intel1
Employee
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Hi,

You can lock the address of any Item by lock shown in the image below:

Capture.PNG

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MMavi
Novice
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Hi,

I solved the problem it was the network address depth of Avalon MM Slave Translator that I used. It was at the default value and I didn't see it for a while. It was larger than the needed address depth and it confused the platform designer somehow.

When I correct it, the problem solved.

 

Thanks anyway for replying.

 

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Ahmed_H_Intel1
Employee
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Good to hear that. I really like your hard working. thanks.

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