I want to use the quartus II RTL-Viewer for documentation purposes, i.e. i want it to create a schematic with corresponding wiring of all the entities i have in my design.Basically it also works, the only thing is that it expands all records and arrays of the connecting signals, so that in the end all wires in the diagramm represent just one bit. Needless to say, this makes the schematic very unclear. However, in the manual for the rtl-viewer it is written that the rtl-viewer actually should be able to group pins and wires into buses "where appropriate". Unfortunately, i could not find any information how to get this feature to work. Does anybody know how to get the rtl-viewer to display buses properly?
this must be a bug/enhancement to the RTL Viewer grouping algorithm, you should report it in a service requesti'd like to see the RTL Viewer get some enhancements that would help with the sort of thing you're doing. for example, the ability to move and lock down modules would be nice
It has had trouble grouping records, especially arrays of records for a long time, and I have raised a defect report. Please raise another yourself as it may encourage them to fix it. It also struggles to cope with multi-dimensional arrays.Its so annoying looking at the RTL viewer when you have a 32x3x3 x18 bit array expanded into individual bits!
Hi, so I see that I'm not the only one with this problem.My problem is because I have 4 blocs with 4 buses of 24 bits. I was looking for a clue if this was a problem with my way of coding, the code works but when I want to document it is impossible to use get good figures from RTL I generate with a for loop generator and I get this: https://www.alteraforum.com/forum/attachment.php?attachmentid=15797 This is useless for documentation, Thanks,