Preserving Unconnected Nets for Signal Tap

[Altera_Forum]

Is there any way of preserving nets that are unconnected to anything other than signal tap? I want to add a counter to monitor another signal that has no other purpose other than viewing in ST.

[Altera_Forum]

I believe that component out ports are always available to be connected to signal tap. Even if the port is not connected. 

If you add a counter as a component to your design I believe the count output should be available to signal tap.   Steve

[Altera_Forum]

From the assignment editor add the assignment "Preserve Fan-out Free Register Node" to the signal you want to preserve. 

 Hope this helps

[Altera_Forum]

That does not work in practice. 

After doing what you suggest in the assignment editor, and rerunning synth&elab, the reg is still not available in Node Finder under any of the Signaltap II filters. It is only available under the post-synthesis filter.  Likewise for when adding /* synthesis syn_noprune */ directive.  Does this capability actually work, or is it just in the manuals?

[Altera_Forum]

--- Quote Start ---  That does not work in practice. After doing what you suggest in the assignment editor, and rerunning synth&elab, the reg is still not available in Node Finder under any of the Signaltap II filters. It is only available under the post-synthesis filter.  Likewise for when adding /* synthesis syn_noprune */ directive.  Does this capability actually work, or is it just in the manuals?  --- Quote End ---     Ive had it working fine. In VHDL - best way to do it is to do this:   noprune VHDL Synthesis Attribute signal reg1: stdlogic; attribute noprune: boolean; attribute noprune of reg1: signal is true;

[Altera_Forum]

The attribute no prune works for sure but there is a second way to do it. 

 If you put signaltap in pre-synthesis mode (after you've done an elaboration) you will be able to selected fanless ouput signals. This has the advantage that if signaltap is not instantiated the node will be synthesised away and wont waste cells and you don't need to do special attribute tricks.  Eg entity port  usefull1  ...  debug_out1 --> unconnected --> connect it to stp if you need it:  Hopefully helpfull

[Altera_Forum]

I have found using the noprune attribute in VHDL doesn't work. However, as the previous post indicates, elaborate the design, then use Signal Tap to add the fanless registers with the pre-synthesis option in SignalTap; then recompile the design, and the fanless registers will be preserved. I have found that this works. -James