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ARach7
Beginner
306 Views

Problem at source files generated by Quartus from user’s “platform design” session (qsys).

 

  1. Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”.
  2.  
  3. Error-[ANALERR_SIZEMISMATCH1] Size mismatch
  4.  
  5. Parameter override type mismatches at various files. Qsys creates wrappers with mismatching types between Verilog and VHDL (attempt to override integer parameter with generic string).
  6.  Error-[OVA1ACTUALTYPEMISMATCH_COMPONENT_ENTITY] Type mismatch

 

 

We have no access to customer files generated by QSYS, and there will not be such access.

All we can provide is an example that gives above errors as follows:

 

%vlogan -sverilog t.v

%vhdlan t.vhd

%vcs tb

 

Top Level Modules:

      tb

Error-[OVA1ACTUALTYPEMISMATCH_COMPONENT_ENTITY] Type mismatch

t.vhd, 16

CHILD

 Line 1.3:

 Please generate .lis file by 'vhdlan -list ...' and see details.

  --+  generic map (AR => AR)

                          ^

 Actual 'AR' is STRING, but formal 'AR' is STD_LOGIC_VECTOR when binding

  component 'CHILD'(t.vhd:15) to entity 'CHILD'(t.v:1).Instance label is

  'UUT'(t.vhd:21).

Error-[ANALERR_SIZEMISMATCH1] Size mismatch

 Mismatch found between the actual named 'DATA', whose type size is 7, and

  the formal named 'DATA', whose type size is 8. Actual 'DATA' is defined in

  COMPONENT named CHILD in file t.vhd at line 18. Formal 'DATA' is defined in

  MODULE named CHILD in file t.v at line 1.

 

 

%cat t.v

module child #(parameter integer ar = 0 ) (input clk, output [7:0] data) ;

endmodule

module tb ();

Ent uut ();

endmodule

 

%cat t.vhd

use STD.textio.all;

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_textio.all;

entity Ent is

end Ent;

Architecture Arc of Ent is

 signal      TP : std_logic ;

 signal      MY_DATA : std_logic_vector (6 downto 0) ;

component CHILD

      generic ( ar : string := "0"          );

       Port (   CLK : In   std_logic;

                 DATA : OUT  std_logic_vector (6 downto 0)   );

  end component;

begin

  UUT : CHILD

      Port Map ( CLK => TP, DATA=>MY_DATA );

end Arc;

 

0 Kudos
5 Replies
AnandRaj_S_Intel
Employee
83 Views

Hi,

 

Can you give more information on

  1. Quartus tool version & edition used?
  2. Device PN?
  3. Full name of the IP used? Also, it's configuration.

 

Regards

Anand

ARach7
Beginner
83 Views

1.quartus_18.1.1.646

 

2.PCIE

 

I have no more info, this issue was observed at 3rd party who tried to use VCS with Quartus.

AnandRaj_S_Intel
Employee
83 Views

​Hi,

 

Check the example from below link, We can't find any Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”.

https://github.com/tatparya/ECE337_Project/tree/master/sourceFiles/amm_master_qsys_with_pcie/synthes...

 

Regards

Anand

ARach7
Beginner
83 Views

​Thanks for the file pointers.

My customer, who is using Quartus with VCS, got the errors I described in this post,  on these files that are used in his Qsys design.

He claims that it is qsys did these mistakes of overriding Verilog parameter "CB_PCIE_MODE" of  module altpciexpav_stif_rx, whose type is the default type  (integer) with value 0, with  VHDL generic of type string, with value "0".

 

Is it possible for Qsys to do such typo, or is it eventually  a user error?

AnandRaj_S_Intel
Employee
83 Views

Hi,

 

No, Qsys can't change its configuration without user inputs(configuration) for an IP.

 

Try by regenerating the Qsys system or creating a simple project with a PCIe IP alone.

 

Regards

Anand

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