We have no access to customer files generated by QSYS, and there will not be such access.
All we can provide is an example that gives above errors as follows:
%vlogan -sverilog t.v
Top Level Modules:
Error-[OVA1ACTUALTYPEMISMATCH_COMPONENT_ENTITY] Type mismatch
Please generate .lis file by 'vhdlan -list ...' and see details.
--+ generic map (AR => AR)
Actual 'AR' is STRING, but formal 'AR' is STD_LOGIC_VECTOR when binding
component 'CHILD'(t.vhd:15) to entity 'CHILD'(t.v:1).Instance label is
Error-[ANALERR_SIZEMISMATCH1] Size mismatch
Mismatch found between the actual named 'DATA', whose type size is 7, and
the formal named 'DATA', whose type size is 8. Actual 'DATA' is defined in
COMPONENT named CHILD in file t.vhd at line 18. Formal 'DATA' is defined in
MODULE named CHILD in file t.v at line 1.
module child #(parameter integer ar = 0 ) (input clk, output [7:0] data) ;
module tb ();
Ent uut ();
entity Ent is
Architecture Arc of Ent is
signal TP : std_logic ;
signal MY_DATA : std_logic_vector (6 downto 0) ;
generic ( ar : string := "0" );
Port ( CLK : In std_logic;
DATA : OUT std_logic_vector (6 downto 0) );
UUT : CHILD
Port Map ( CLK => TP, DATA=>MY_DATA );
Check the example from below link, We can't find any Port connection width mismatches at 2 altera pcie files, “altpciexpav_stif_rx.v” and “altpciexpav_stif_tx.v”.
Thanks for the file pointers.
My customer, who is using Quartus with VCS, got the errors I described in this post, on these files that are used in his Qsys design.
He claims that it is qsys did these mistakes of overriding Verilog parameter "CB_PCIE_MODE" of module altpciexpav_stif_rx, whose type is the default type (integer) with value 0, with VHDL generic of type string, with value "0".
Is it possible for Qsys to do such typo, or is it eventually a user error?
No, Qsys can't change its configuration without user inputs(configuration) for an IP.
Try by regenerating the Qsys system or creating a simple project with a PCIe IP alone.