Problem simulating Verilog ip catalog uart with my VHDL design using Modelsim Altera starter edition

[JTUCK3]

The IP catalog seems to generate Verilog, even though I ask for VHDL. It appears to create a top level VHDL wrapper for its Verilog design. As I'm using VHDL for my design, I get a simulation error "ALTERA version supports only a single HDL". Does this mean I can't use any IP from the IP catalog if I'm designing in VHDL as the simulator only allows one language?

[Abe]

My guesses are that the ModelSim starter edition does not allow Mixed language simulation, ie, VHDL and Verilog mixed designs. You may need to get the subscription version for mixed language simulations.

Try generating the IP again and if the issue persists, i suggest contacting Intel support directly.

[JTUCK3]

Thanks Abraham, that would be my guess.

I was also questioning why the IP catalog can't generate its IP in VHDL. The Parameter Editor has a tick box - Verilog or VHDL - but that's not actually what it does.

[Tricky]

What version are you using? Modelsim starter has supported mixed language for a few versions.

Also​, a lot of IP is developed only in sv now, and developing dual language versions is not happening, a vhdl wrapper is the best you're likely to get. Xilinx won't even provide the wrappers in. Vhdl now.