Problem with ALTPLL

[Altera_Forum]

I use a ATLPLL IP In my design. This PLL has one input clock and one output clock. 

The input clock is 62.5MHz. The PLL outputs an inverted clock. I expected the clock max skew from inclk0(62.5MHz) to c0(inverted) is 0.5ns. The post-sim waveform shows the skew is 10.7ns. The ALTPLL's connections as below: DPLL U_DPLL(  .inclk0 (clk_62M ),  .c0 (clk_62M_inv),  .locked (locked )  ); What's wrong with my design?  Any and all help is very much appreciated Harris

[Altera_Forum]

Is PLL output configured as source synchronous?

[Altera_Forum]

How to configure the PLL's output? 

Thanks

[Altera_Forum]

Quartus II MegaWizard Plug-In Manager

[Altera_Forum]

OK 

I will try it. Thanks

[Altera_Forum]

I have changed the PLL settings, but the problem is still exist. 

My PLL current settings:  1. Use the feedback path inside the PLL 2. In normal mode 3. The source synchronous compensation mode si disabled by Quartus II  The c0 is used internal. Thanks

[Altera_Forum]

I believe Cris suggets to set it to source synchronous mode instead of normal mode (tick the selection just under normal mode)

[Altera_Forum]

The option In source-synchronous compensation mode is disabled by Quartus II.  

I can not tick the selection. My device is Cyclone. Thanks