Problem with Clocks

[Altera_Forum]

Hi all, 

 I have following problem. I hafe two clocks on FPGA input, lets say A and B. They are exactly the same and go through PLLs. Clock A feeds a queue which provides data to two registers RA and RB. These registers are clocked with clock A and B correspondingly. The problem is that I have timing violation (setup and hold) on register RB. How can I avoid it or how can I constraint TimeQuest appropriately ?  Best regards  Joel

[Altera_Forum]

hi joel what xactly the path u have provided for the register RB when compared to register RA.. then u can get to the point u need..

[Altera_Forum]

--- Quote Start ---  Hi all,  I have following problem. I hafe two clocks on FPGA input, lets say A and B. They are exactly the same and go through PLLs. Clock A feeds a queue which provides data to two registers RA and RB. These registers are clocked with clock A and B correspondingly. The problem is that I have timing violation (setup and hold) on register RB. How can I avoid it or how can I constraint TimeQuest appropriately ?  Best regards  Joel  --- Quote End ---    Hi Joel,  "They are exactly the same and go through PLLs. " Why did you use two clocks ?  Kind regards  GPK