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I want to configure FIR II filter to convert 15 MSPS data to 15.36 MSPS data. In order to do this Interpolation factor should be 128 and decimation factor should be 125. I have described the same below diagram:
But when I try to configure FIR II IP I am getting below errors:
Error: gj: Cannot have fewer taps than the amount of interpolation
Error: gj: Output Fractional Full Bit Width should greater than Output Fractional bit width
Error: gj: Output Bit Width should be greater than 1
Error: gj: Port ast_sink_data is not fully defined after elaboration
Info: gj: PhysChanIn -1, PhysChanOut -1, ChansPerPhyIn -1, ChansPerPhyOut -1, OutputFullBitWidth -1, Bankcount 1, CoefBitWidth 8
Filter specification settings:
Coefficient settings is as below:
input output parameters are as below
Please guide me to resolve this error to get the IP working.
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Hi,
Sorry for the delay. By merely looking at the error message, it seems like the specific configuration that you are selecting are not a valid combination by the IP. Please allow me some time to further look into this and get back to you.
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Hi,
Sorry for the delay. I have performing different tests to narrow down the problem. I found that the errors are related to the number of coeff taps are not sufficient to achieve your interpolation. I have tested increasing the coeff no. in the "Coefficients" tab of the IP Editor to a dummy amount of 147 and the errors go away. Sorry as I am not a FIR specialist and could not really comment the right coeff no. to use for your specific case. You might need to further explore into this.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Hello all,
I am also following same issue.
Is there any document or method for considering or calculating number of taps for FIR filter.
In the IP if we import coefficient file it will automatically shows the error is gone (as @CheePin_C_Intel mentioned )
Thank you
Regards
Pavan
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Hi,
Regarding your inquiry on how to calculate the tap for FIR filter, it would be more toward design implementation inquiry. Sorry as I am not really a design specialist and could not provide any helpful comment on this. Sorry for the inconvenience.
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Hi,
I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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