Problem with tri-state controller

[Altera_Forum]

Hi everyone! 

I'm trying to use tri-state controller to connect nios2 system to w5300 chip (w5300 is considered as SRAM). Write command works very strange: two nWR pulses and two nCS are formed, so two write operations are executed. Address value stays the same during both write operations, but data changes to all zeros before second operation, so firstly correct value is written into SRAM, but then controller writes zero to the same address. If I change some timing options (setup time=0, write wait time=0, data hold time=0) only one pair of nCS/nWR pulses is formed, but these changed timing options don't correspond to required write diagram. Has anybody faced this issue?

[Altera_Forum]

are the byte enable signals the same on both accesses? Weird things can happen sometime on those, especially if the CPU is doing a 8 or 16-bit access, or if the memory is not 32 bits wide. Sometimes you get extra write accesses with all the byte enable signals deasserted.

[Altera_Forum]

Byteenable is "11" during both write operations, data bus width is 16 bits. It seems that acceptable decision is to change controller data width to 32 bits and use just 16 low bits. At least I haven't noticed any problems with it so far.

[Altera_Forum]

Whenever possible, yes it's a lot better to try to stick to 32 bit to avoid weird issues with the automatic width adapters.