Problems probably related to signal propagation (timeQuest questions)

[Altera_Forum]

Hi, I have a Terasic DE-10lite board (MAX10 based) and I have designed a controller (in verilog) for the SDRAM on the board. Simulating the project with modelsim, the controller behaves exactly as i would (the timing accurately reflects those on the SDRAM datasheet) but programming the board I can not perform any operation on sdram (i'm using a vga monitor for output). When compiling, I see a "Timing requirements not met" warning, which makes me think there is some problem with signal propagation on the board. Reading something online I've seen that the problem could come from here; I tried to use timequest timing analyzer but I do not know how to move inside it. Launching some reports, I got some errors regarding the slack, the end point TNS (what is the latter?) and the clock. Also, by analyzing the Fmax I get a frequency much lower than my 100MHz. How can I perform an in-depth analysis of the signals so I can understand how to optimize my design? What advice can you give me? I attach screenshots and, if needed, I attach the source code. Thanks to all. 

    compilation log (http://goo.gl/saj44x) 

[Altera_Forum]

The timing will come from the design, and not fixable in timequest. Timequest can identify where the problems are. 

 If you post some code, maybe we can give you an idea of what the problems might be.  Another thing.. did you provide an sdc file? If you don't provide timing specs, it will default to try and achieve 1000mhz. This is very over constrained and can cause it to give up early. You might get a small improvement with realistic timing specs.

[Altera_Forum]

Hi Tricky, thanks for the reply. I use an sdc file with some timing specs. I attach the verilog file that i used and the sdc file.  

 bit.ly/sdram_vga-v (http://bit.ly/sdram_vga-v) (top module) bit.ly/sdram_controller-v (http://bit.ly/sdram_controller-v) bit.ly/sdram_vga-sdc (http://bit.ly/sdram_controller-v)  Thanks to all.