Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16637 Discussions

Project Creation Error in HDL Workflow Advisor

Sawicki
Novice
‎07-30-2021 03:11 AM
1,097 Views
Solved Jump to solution

Iam following Mathworks guide on HDL coder. But in HDL Workflow Advisor project creation under Embadded System Integration task that I launch fails.

Failed Create Project.

Task "Create Project" unsuccessful. See log for details.
Generated logfile: C:\Users\user\Documents\MATLAB\hdlv3\hdlsrc\hdlcoder_led_blinking_4bit\workflow_task_CreateProject.log
Info: *******************************************************************
Info: Running Quartus Prime Shell
    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
    Info: Copyright (C) 2019  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and any partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details, at
    Info: https://fpgasoftware.intel.com/eula.
    Info: Processing started: Fri Jul 30 12:02:21 2021
Info: Command: quartus_sh -t quartus_create_prj.tcl
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
    Info: Processing started: Fri Jul 30 12:02:25 2021
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off system -c system --plan
Info: qfit2_default_script.tcl version: #1
Info: Project  = system
Info: Revision = system
Warning (11747): Analysis and Synthesis (quartus_map) with top-level entity name "system" was not run before running I/O Assignment Analysis -- I/O Assignment Analysis will check only I/O assignments on the reserved pins
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (119006): Selected device 5CSXFC6D6F31C8 for design "system"
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (184020): Starting Fitter periphery placement operations
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:16
Info: Quartus Prime I/O Assignment Analysis was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 5443 megabytes
    Info: Processing ended: Fri Jul 30 12:02:42 2021
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:18

INFO: Quartus license check was successful.

Info (125061): Changed top-level design entity name to "system_soc"
Info (23030): Evaluation of Tcl script quartus_create_prj.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 4701 megabytes
    Info: Processing ended: Fri Jul 30 12:02:46 2021
    Info: Elapsed time: 00:00:25
    Info: Total CPU time (on all processors): 00:00:06

Elapsed time is 25.0184 seconds.
2021.07.30.12:02:46 Info: Doing: <b>qsys-script --script=qsys_create_system.tcl</b>
2021.07.30.12:02:52 Info: load_system system_soc.qsys
2021.07.30.12:03:12 Info: set_project_property DEVICE_FAMILY Cyclone V
2021.07.30.12:03:12 Info: set_project_property DEVICE 5CSXFC6D6F31C8
2021.07.30.12:03:22 Info: validate_system 
2021.07.30.12:03:22 Info: save_system system_soc.qsys

Elapsed time is 36.4763 seconds.
2021.07.30.12:03:23 Info: Doing: <b>qsys-script --script=qsys_insert_ip.tcl</b>
2021.07.30.12:03:30 Info: load_system system_soc.qsys
2021.07.30.12:03:53 Info: add_instance led_count_ip_0 led_count_ip 1.0
2021.07.30.12:03:53 Info: add_connection pll_0.outclk0 led_count_ip_0.ip_clk
2021.07.30.12:03:53 Info: add_connection hps_0.h2f_reset led_count_ip_0.ip_rst
2021.07.30.12:03:53 Info: set_instance_parameter_value pll_0 gui_output_clock_frequency0 50.000000
2021.07.30.12:03:53 Info: add_connection hps_0.h2f_axi_master led_count_ip_0.s_axi
2021.07.30.12:03:53 Info: set_connection_parameter_value hps_0.h2f_axi_master/led_count_ip_0.s_axi baseAddress 0x0000
2021.07.30.12:03:53 Info: add_connection pll_0.outclk0 led_count_ip_0.axi_clk
2021.07.30.12:03:53 Info: add_connection hps_0.h2f_reset led_count_ip_0.axi_reset
2021.07.30.12:03:53 Info: add_interface led_count_ip_0_GPLED conduit end
2021.07.30.12:03:53 Info: set_interface_property led_count_ip_0_GPLED EXPORT_OF led_count_ip_0.GPLED
2021.07.30.12:03:53 Info: validate_system 
2021.07.30.12:03:53 Info: save_system system_soc.qsys

Elapsed time is 30.6205 seconds.
2021.07.30.12:04:26 Info: Saving generation log to C:/Users/user/Documents/MATLAB/hdlv3/quartus_prj/qsys_prj/system_soc/system_soc_generation.rpt
2021.07.30.12:04:26 Info: Starting: <b>Create HDL design files for synthesis</b>
2021.07.30.12:04:26 Info: qsys-generate C:\Users\user\Documents\MATLAB\hdlv3\quartus_prj\qsys_prj\system_soc.qsys --synthesis=VERILOG --output-directory=C:\Users\user\Documents\MATLAB\hdlv3\quartus_prj\qsys_prj\system_soc\synthesis --family="Cyclone V" --part=5CSXFC6D6F31C8
2021.07.30.12:04:26 Info: Loading qsys_prj/system_soc.qsys
2021.07.30.12:04:27 Info: Reading input file
2021.07.30.12:04:27 Info: Adding hps_0 [altera_hps 19.1]
2021.07.30.12:04:27 Info: Parameterizing module hps_0
2021.07.30.12:04:27 Info: Adding led_count_ip_0 [led_count_ip 1.0]
2021.07.30.12:04:27 Info: Parameterizing module led_count_ip_0
2021.07.30.12:04:27 Info: Adding pll_0 [altera_pll 19.1]
2021.07.30.12:04:27 Info: Parameterizing module pll_0
2021.07.30.12:04:27 Info: Building connections
2021.07.30.12:04:27 Info: Parameterizing connections
2021.07.30.12:04:27 Info: Validating
2021.07.30.12:04:38 Info: Done reading input file
2021.07.30.12:04:42 Info: system_soc.hps_0: HPS Main PLL counter settings: n = 0  m = 47
2021.07.30.12:04:42 Info: system_soc.hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
2021.07.30.12:04:42 Info: system_soc.pll_0: The legal reference clock frequency is 5.0 MHz..650.0 MHz
2021.07.30.12:04:42 Info: system_soc.pll_0: Able to implement PLL with user settings
2021.07.30.12:04:46 Info: system_soc: Generating <b>system_soc</b> "<b>system_soc</b>" for QUARTUS_SYNTH
2021.07.30.12:04:52 Info: Interconnect is inserted between master hps_0.h2f_axi_master and slave led_count_ip_0.s_axi because the master is of type axi and the slave is of type axi4.
2021.07.30.12:04:52 Warning: hps_0.f2h_irq0: Cannot connect clock for <b>irq_mapper.sender</b>
2021.07.30.12:04:52 Warning: hps_0.f2h_irq0: Cannot connect reset for <b>irq_mapper.sender</b>
2021.07.30.12:04:52 Warning: hps_0.f2h_irq1: Cannot connect clock for <b>irq_mapper_001.sender</b>
2021.07.30.12:04:52 Warning: hps_0.f2h_irq1: Cannot connect reset for <b>irq_mapper_001.sender</b>
2021.07.30.12:04:57 Info: hps_0: "Running  for module: hps_0"
2021.07.30.12:04:58 Info: hps_0: HPS Main PLL counter settings: n = 0  m = 47
2021.07.30.12:04:59 Info: hps_0: HPS peripherial PLL counter settings: n = 0  m = 39
2021.07.30.12:05:02 Info: hps_0: "<b>system_soc</b>" instantiated <b>altera_hps</b> "<b>hps_0</b>"
2021.07.30.12:05:02 Info: led_count_ip_0: "<b>system_soc</b>" instantiated <b>led_count_ip</b> "<b>led_count_ip_0</b>"
2021.07.30.12:05:02 Info: pll_0: "<b>system_soc</b>" instantiated <b>altera_pll</b> "<b>pll_0</b>"
2021.07.30.12:05:04 Info: mm_interconnect_0: "<b>system_soc</b>" instantiated <b>altera_mm_interconnect</b> "<b>mm_interconnect_0</b>"
2021.07.30.12:05:04 Info: irq_mapper: "<b>system_soc</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
2021.07.30.12:05:04 Info: rst_controller: "<b>system_soc</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"
2021.07.30.12:05:04 Info: fpga_interfaces: "<b>hps_0</b>" instantiated <b>altera_interface_generator</b> "<b>fpga_interfaces</b>"
2021.07.30.12:05:05 Info: hps_io: "<b>hps_0</b>" instantiated <b>altera_hps_io</b> "<b>hps_io</b>"
2021.07.30.12:05:05 Info: led_count_ip_0_s_axi_translator: "<b>mm_interconnect_0</b>" instantiated <b>altera_merlin_axi_translator</b> "<b>led_count_ip_0_s_axi_translator</b>"
2021.07.30.12:05:30 Error: border: Error during execution of script generate_hps_sdram.tcl: seq: FATAL: Cannot generate IP in a Windows evironment!
2021.07.30.12:05:30 Error: border: Error during execution of script generate_hps_sdram.tcl: seq: An error occurred
2021.07.30.12:05:30 Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 3 or more modules remaining
2021.07.30.12:05:30 Error: border: Execution of script generate_hps_sdram.tcl failed
2021.07.30.12:05:30 Error: border: ERROR: FATAL: Cannot generate IP in a Windows evironment!
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:06 Info:
2021.07.30.12:05:30 Error: border: ********************************************************************************************************************
2021.07.30.12:05:30 Error: border: 
2021.07.30.12:05:30 Error: border: Use qsys-generate for a simpler command-line interface for generating IP.
2021.07.30.12:05:30 Error: border: 
2021.07.30.12:05:30 Error: border: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
2021.07.30.12:05:30 Error: border: 
2021.07.30.12:05:30 Error: border: ********************************************************************************************************************
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:11 Warning: Ignored parameter assignment device=5CSXFC6D6F31C8
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:11 Warning: Ignored parameter assignment extended_family_support=true
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram.seq: This module has no ports or interfaces
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram.p0: p0.scc must be exported, or connected to a matching conduit.
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram.as: as.afi_init_cal_req must be exported, or connected to a matching conduit.
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram.as: as.tracking must be exported, or connected to a matching conduit.
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram.c0: c0.status must be exported, or connected to a matching conduit.
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Warning: hps_sdram.p0: p0.avl must be connected to an Avalon-MM master
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:19 Info: hps_sdram: Generating altera_mem_if_hps_emif "hps_sdram" for QUARTUS_SYNTH
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:21 Info: pll: "hps_sdram" instantiated altera_mem_if_hps_pll "pll"
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:21 Info: p0: Generating clock pair generator
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:22 Info: p0: Generating hps_sdram_p0_altdqdqs
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0:
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0: *****************************
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0:
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0: Remember to run the hps_sdram_p0_pin_assignments.tcl
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0: script after running Synthesis and before Fitting.
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0:
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0: *****************************
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0:
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Error: seq: FATAL: Cannot generate IP in a Windows evironment!
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Error: seq: An error occurred
2021.07.30.12:05:30 Error: border: while executing
2021.07.30.12:05:30 Error: border: "error "An error occurred""
2021.07.30.12:05:30 Error: border: (procedure "_error" line 8)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "_error "FATAL: Cannot generate IP in a Windows evironment!""
2021.07.30.12:05:30 Error: border: ("if" then script line 2)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "if { $OS_WIN == 1} {
2021.07.30.12:05:30 Error: border: _error "FATAL: Cannot generate IP in a Windows evironment!"
2021.07.30.12:05:30 Error: border: return ""
2021.07.30.12:05:30 Error: border: }"
2021.07.30.12:05:30 Error: border: (procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer_sw" line 22)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer_sw $prefix $protocol $tmpdir $fileset {} $rdimm $lrdimm $mem_size $mem_size  "${prefix}_sequencer..."
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "set return_files_sw [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer_sw $prefix $protocol $tmpdir $fileset {} $rdimm $lrdimm $mem_size $mem_size ..."
2021.07.30.12:05:30 Error: border: (procedure "generate_sw" line 16)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "generate_sw $name $fileset"
2021.07.30.12:05:30 Error: border: ("if" then script line 4)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "if {[string compare -nocase $fileset QUARTUS_SYNTH] == 0} {
2021.07.30.12:05:30 Error: border: 		set top_level_file "altera_mem_if_hhp_qseq_synth_top.v"
2021.07.30.12:05:30 Error: border: 		add_fileset_file $top_level_fi..."
2021.07.30.12:05:30 Error: border: (procedure "generate_files" line 4)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "generate_files $name QUARTUS_SYNTH"
2021.07.30.12:05:30 Error: border: (procedure "generate_synth" line 3)
2021.07.30.12:05:30 Error: border: invoked from within
2021.07.30.12:05:30 Error: border: "generate_synth altera_mem_if_hhp_qseq_synth_top"
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: seq: "hps_sdram" instantiated altera_mem_if_hhp_ddr3_qseq "seq"
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Error: Generation stopped, 3 or more modules remaining
2021.07.30.12:05:30 Error: border: 2021.07.30.12:05:30 Info: hps_sdram: Done "hps_sdram" with 7 modules, 24 files
2021.07.30.12:05:30 Info: border: "<b>hps_io</b>" instantiated <b>altera_interface_generator</b> "<b>border</b>"
2021.07.30.12:05:31 Info: system_soc: Done "<b>system_soc</b>" with 11 modules, 52 files
2021.07.30.12:05:31 Error: qsys-generate failed with exit code 1: 70 Errors, 4 Warnings
2021.07.30.12:05:31 Info: Finished: <b>Create HDL design files for synthesis</b>

Elapsed time is 98.049 seconds.

 I tried changing HDL Code Generation Settings to Verilog instead of VHDL but nothing changed. Iam using Quartus 19.1 and got Cyclone V libraries instaled. OS: Windows 10, Matlab R2021a.

Iam including error log file

workflow_task_CreateProject.log
0 Kudos
1 Solution
Sawicki
Novice
‎08-03-2021 12:31 AM
1,069 Views
Solved Jump to solution

Fixed the issue. The solution steps are:

>Using Intel Quartus Prime 19.1 (patched)

>Instaling ubuntu 18.04 LTS and manualy instaling WSL, make and dos2unix (after updating apt package list)

>Enabling WSL in windows control panel

 

 

View solution in original post

0 Kudos
Copy link

Link Copied

2 Replies
Sawicki
Novice
‎08-03-2021 12:31 AM
1,070 Views
Solved Jump to solution

Fixed the issue. The solution steps are:

>Using Intel Quartus Prime 19.1 (patched)

>Instaling ubuntu 18.04 LTS and manualy instaling WSL, make and dos2unix (after updating apt package list)

>Enabling WSL in windows control panel

 

 

0 Kudos
Copy link
RightSaidFred
Beginner
‎08-27-2022 12:41 PM
800 Views
Solved Jump to solution

Hi,

have the same issue and like to try this solution. Here can i find this patch and is it posible to use ubuntu 20.04 LTS and wsl2? 

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.