QII 8.0SP1 gives Error 10028 with SystemVerilog using modport

[Altera_Forum]

Hi All, 

 I am trying to synthesize several SystemVerilog modules that declare interfaces and then use them to connect to each other.  One interface module shows Error 10028 : Can't resolve multiple constant drivers for net reset  In the interface module somebody declares:  logic reset;  and then in the same interface modules two modports are declared that use reset as output:  modport drive (output reset...)  modport bus_drive (output reset...)  I am including the interface module as part of the SystemVerilog files to compile in the Project Navigator Files.  Is this a true SystemVerilog syntax error or is Quartus II 8.0SP1 getting confused with good SystemVerilog coding?  Thanks,  RAUL

[Altera_Forum]

Yes, this is the way Quartus behaves. When you declare a modport with an output, that modport output is considered to be a driver of the interface signal, even if that modport is never instantiated. 

 I am not sure whether this is a bug or legal behaviour, but either way, it stinks.  Only one modport may be declared with an output for a given signal, and then that modport MUST be used to drive that signal. If the modport is never instantiated, and the signal is driven by direct assignment to the interface net instead, then Quartus complains about multiple drivers.  I have found no workaround for this, other than to design your interfaces with this in mind. This can be somewhat difficult though, as the interface is then required to know something about the hierarchy structure in which it is used. Like i said, it stinks.

[Altera_Forum]

Thanks, I just also found out that I need to separate the interface declarations into two separate files each one with one output to be able to proceed in synthesis. So in the end I have: 

 if1.sv ======== interface if1... logic reset; modport rcv1 (output reset... =======  if2.sv ======== interface if2... logic reset; modport rcv2 (output reset...) ============  vs. before  if.sv =========== interface if...  logic reset;  modport rcv1 (output reset...)  modport rcv2 (output reset...) =========  Thanks for the prompt reply.

[Altera_Forum]

It's more to do with the way QIS models modports during synthesis. You could call it a bug, but it's certainly not a behavior demanded by the standard. I suggest trying Quartus II 8.1 when it comes out in another month or so.

[Altera_Forum]

Thanks, I will definitely try QII 8.1.

[Altera_Forum]

Quartus is extremely picky about interfaces and modports. Still much better than other vendors that don't support System Verilog at all. 

 Pugmedia, are you sure you need to use two separate files? That doesn't make sense. Did you try two separate interfaces, but in the same file?

[Altera_Forum]

Hi vjAlter, 

 Yes, two different interfaces would work too as long as the output name is different.  I agree that the current level of support is better than nothing at all but not being on par with Synopsys tools makes it hard to run ASIC code on FPGAs.  RAUL