Being more comfortable with VHDL, I asked Qsys to generate the simulation for my (fairly complex) Qsys system in VHDL. I force quit after over twenty minutes. Then I tried it in Verilog. It took a minute and a half.
VHDL is admittedly more verbose than Verilog, but come on. Also, the VHDL simulation seems to have generated many, many more files.
I'm on Quartus Prime 15.1, running on 64-bit CentOS 6.7. Anyone else seeing this kind of behavior?
